Dual performance trim for optimization of non-volatile memory performance, endurance, and reliability

1. A non-volatile memory device, comprising:

a control circuit configured to connect to one or more arrays, each array comprising a plurality of blocks each of a plurality of non-volatile memory cells, the control circuit configured to:

receive a write command to program a first set of data to a first of the one or more arrays in a first format;

determine whether the write command is a host write command;

in response to determining that the write command is a host write command, write the first set of data into the first array in the first format using a first programming algorithm;

determine whether the write command is a background write command;

in response to determining that the write command is a background write command, write the first set of data into the first array in the first format using a second programming algorithm, the second programming algorithm being of a slower write speed than the first programming algorithm; and

maintain, for each of the blocks of the first array, a count of a number of program/erase cycles experienced by the block, where a write to the block using the first programming algorithm is weighted more in the count than a write to the block using the second programming algorithm.

2. The non-volatile memory device of claim 1 , wherein the control circuit is formed on a control die, the non-volatile memory device further comprising:

a memory die including the first array, the memory die formed separately from and bonded to the control die.

3. The non-volatile memory device of claim 1 , wherein the control circuit receives the write command from a memory controller and the write commend specifies whether the write command is the host write command or the background write command.

4. The non-volatile memory device of claim 3 , further comprising:

the memory controller, wherein the memory controller is configured to generate the host write command in response to a request from a host and to generate the background write command internally.

5. The non-volatile memory device of claim 4 ,

wherein the memory controller is configured to generate the background write command based on values of the counts.

6. The non-volatile memory device of claim 1 , wherein first set of data for the background write command is read from one or more of the arrays other than the first array.

7. The non-volatile memory device of claim 1 , wherein the control circuit is further configured to:

maintain a first set of programming parameters for the first programming algorithm in a register memory; and

maintain a second set of programming parameters for the second programming algorithm in the register memory.

8. The non-volatile memory device of claim 1 , wherein the first format is a multi-bit per cell data format.

9. The non-volatile memory device of claim 1 , wherein:

the first programming algorithm applies a first staircase waveform to selected memory cells; and

the second programming algorithm applies a second staircase waveform to the selected memory cells, where first staircase waveform has a larger step size than the second staircase waveform.

10. The non-volatile memory device of claim 9 , wherein:

a first step of the first staircase waveform is of a higher voltage level than a first step of the second staircase waveform.

11. The non-volatile memory device of claim 1 , wherein:

the first programming algorithm uses a different set of program verify levels than the second programming algorithm.

12. A method, comprising:

maintaining, by a non-volatile memory device comprising an array having a plurality of blocks each of a plurality of non-volatile memory cells, an experience count for a number of program/erase cycles experienced by each of the blocks;

receiving at the non-volatile memory device one or more commands to write data to a first of the blocks;

determining for each of the one or more commands to write data to the first block whether the data is to be written according to a first programming algorithm or a second programming algorithm, the second programming algorithm being of a slower write speed than the first programming algorithm;

in response to determining that the data is to be written to the first block according to the first programming algorithm, writing the data to the first block using the first programming algorithm and incrementing the experience count maintained for the first block by a first amount; and

in response to determining that the data is to be written to the first block according to the second programming algorithm, writing the data to the first block using the first programming algorithm and incrementing the experience count maintained for the first block by a second amount, the second amount being less that first amount.

13. The method of claim 12 , wherein:

the one or more commands for which the data is to be written according to the first programming algorithm are host write commands, and

the one or more commands for which the data is to be written according to the second programming algorithm are background operation commands.

14. The method of claim 13 , wherein:

generating the host write commands by a memory controller is in response to a write request received from a host; and

generating the background operation commands internally by the memory controller.

15. The method of claim 14 , further comprising:

receiving the experience counts by the memory controller; and

generating the background commands by the memory controller based on values of the received experience counts.

16. The method of claim 12 , wherein:

writing the data to the first block using the first programming algorithm comprises applying a first staircase waveform to selected memory cells; and

writing the data to the first block using the second programming algorithm comprises applying a second staircase waveform to the selected memory cells, where first staircase waveform has a larger step size than the second staircase waveform.

17. A system, comprising:

a memory controller configured to receive data write commands from a host and to internally generate background write commands; and

a plurality of non-volatile memory devices configured to receive and execute commands from the memory controller, each of the non-volatile memory devices comprising:

one or more arrays non-volatile of memory cells, each array comprising a plurality of blocks each of a plurality of the non-volatile memory cells; and

one or more control circuits connected to the one or more arrays and configured to:

receive a write command to program a first set of data to a first of the one or more arrays in a first format;

determine whether the write command is a data write command from the host;

in response to determining that the write command is a write command from the host, write the first set of data into the first array in the first format using a first programming algorithm;

determine whether the write command is a background write command; and

in response to determining that the write command is a background write command, write the first set of data into the first array in the first format using a second programming algorithm, the second programming algorithm being of a slower write speed than the first programming algorithm.

18. The system of claim 17 , wherein the one or more control circuits are further configured to:

maintain, for each of the blocks of the first array, a count of a number of program/erase cycles experienced by the block, wherein a write to the block using the first programming algorithm is weighted more in the count than a write to the block using the second programming algorithm.

19. The system of claim 18 , wherein the memory controller is configured to generate the background write command based on values of the counts.

20. The system of claim 17 , wherein:

the first programming algorithm applies a first staircase waveform to selected memory cells; and

the second programming algorithm applies a second staircase waveform to the selected memory cells, where first staircase waveform has a larger step size than the second staircase waveform.