IP Library Granted Patent US 10,496,334
Granted Patent B2
US 10,496,334 · App. 15/971,869 · Granted Dec 3, 2019

Solid state drive using two-level indirection architecture

Inventors: Mark David Myran (Trabuco Canyon, CA); Chandan Mishra (Irvine, CA); Amir Hossein Gholamipour (Anaheim, CA); Aldo Giovanni Cometti (San Diego, CA); Namhoon Yoo (Anaheim, CA)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G06F3/0659G06F3/0604G06F3/0688G06F12/0246G06F12/1009G06F2212/1008G06F2212/657
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Quick Facts
Patent No.
US 10,496,334
App. No.
15/971,869
Granted
Dec 3, 2019
Kind
B2
Abstract

Aspects of the present disclosure provide systems and methods for operating a solid state drive (SSD) using two-level indirection architecture. The SSD receives a command to perform a data operation in a NAND array and a logical address for the data operation. The SSD then converts the logical address to a physical address using a two-stage logical-to-physical (L2P) mapping table that includes a first stage stored in a byte-rewritable memory and a second stage stored in a block-erasable non-volatile memory (NVM). The SSD performs the data operation in the NAND array based on the physical address. The byte-rewritable memory may any byte-rewritable persistent memory. The block-erasable low latency NVM may be a flash memory that has lower latency than NAND array.

Claims (80)

1. A method of operating a solid state drive (SSD), comprising:

receiving a command to perform a data operation in a NAND array and a logical address for the data operation;

converting the logical address to a physical address using a two-stage logical-to-physical (L2P) mapping table comprising a partition table stored in a byte-rewritable non-volatile memory and a plurality of L2P table partitions stored in a block-erasable non-volatile memory (NVM) that has faster access than the NAND array; and

performing the data operation in the NAND array based on the physical address.

2. The method of claim 1 ,

wherein the converting comprises:

determining, using the partition table, a location in the block-erasable NVM storing the L2P table partition corresponding to the logical address for the data operation; and

determining, using the L2P table partition, the physical address for performing the data operation in the NAND array.

3. The method of claim 2 , wherein the performing the data operation comprises:

programming second data, received as part of the command, to the NAND array to replace first data stored in the NAND array; and

updating the partition table and the L2P table partition to map the logical address to a physical address of the second data.

4. The method of claim 3 , wherein the updating comprises:

updating an L2P entry in the L2P table partition to store the physical address of the second data; and

updating an entry in the partition table to store a new location of the updated L2P table partition.

5. The method of claim 1 , wherein the command comprises, at least one of:

a program command for writing data to a page of the NAND array; or

a read command for reading data from a page of the NAND array.

6. The method of claim 1 , wherein:

the partition table comprises a plurality of partition indexes,

wherein each partition index indicates a location of a corresponding one of the L2P table partitions in the block-erasable NVM.

7. A solid state device (SSD) comprising:

a communication interface configured to communicate with a host;

a NAND array;

a byte-rewritable non-volatile memory;

a block-erasable non-volatile memory (NVM) that has faster access than the NAND array; and

a controller operatively coupled with the communication interface and the NAND array, wherein the controller is configured to:

receive, from the host, a command to perform a data operation in the NAND array and a logical address for the data operation;

convert the logical address to a physical address using a two-stage logical-to-physical (L2P) mapping table comprising a partition table stored in the byte-rewritable non-volatile memory and a plurality of L2P table partitions stored in the block-erasable NVM; and

perform the data operation in the NAND array based on the physical address.

8. The SSD of claim 7 ,

wherein the controller is further configured to:

determine, using the partition table, a location in the block-erasable NVM storing the L2P table partition corresponding to the logical address for the data operation; and

determine, using the L2P table partition, the physical address for performing the data operation in the NAND array.

9. The SSD of claim 8 , wherein the controller is further configured to:

program second data, received as part of the command, to the NAND array to replace first data stored in the NAND array; and

update the partition table and the L2P table partition to map the logical address to a physical address of the second data.

10. The SSD of claim 9 , wherein the controller is further configured to:

update an L2P entry in the L2P table partition to store the physical address of the second data; and

update an entry in the partition table to store a new location of the updated L2P table partition.

11. The SSD of claim 7 , wherein the command comprises, at least one of:

a program command for writing data to a page of the NAND array; or

a read command for reading data from a page of the NAND array.

12. The SSD of claim 7 , wherein:

the partition table comprises a plurality of partition indexes,

and wherein each partition index indicates a location of a corresponding one of the L2P table partitions in the block-erasable NVM.

13. A solid state drive (SSD), comprising:

means for receiving a command to perform a data operation in a NAND array and a logical address for the data operation;

means for converting the logical address to a physical address using a two-stage logical-to-physical (L2P) mapping table comprising a partition table stored in a byte-rewritable non-volatile memory and a plurality of L2P table partitions stored in a block-erasable non-volatile memory (NVM) that has faster access than the NAND array; and

means for performing the data operation in the NAND array based on the physical address.

14. The SSD of claim 13 ,

wherein the means for converting is configured to:

determine, using the partition table a location in the block-erasable NVM storing the L2P table partition corresponding to the logical address for the data operation; and

determine, using the L2P table partition, the physical address for performing the data operation in the NAND array.

15. The SSD of claim 14 , wherein the means for performing the data operation is configured to:

program second data to the NAND array to replace first data stored in the NAND array; and

update the partition table and the L2P table partition to map the logical address to a physical address of the second data.

16. The SSD of claim 15 , wherein the means for performing the data operation is further configured to:

update an L2P entry in the L2P table partition to store the physical address of the second data; and

update an entry in the partition table to store a new location of the updated L2P table partition.

17. The SSD of claim 13 , wherein the command comprises, at least one of:

a program command for writing data to a page of the NAND array; or

a read command for reading data from a page of the NAND array.

18. The SSD of claim 13 , wherein:

the partition table comprises a plurality of partition indexes,

wherein each partition index indicates a location of a corresponding one of the L2P table partitions in the block-erasable NVM.

19. A solid state drive (SSD) comprising:

a NAND array;

a byte-rewritable non-volatile memory;

a block-erasable non-volatile memory (NVM) that has faster access than the NAND array; and

a controller operatively coupled with the NAND array, the byte-rewritable non-volatile memory, and the block-erasable NVM,

wherein the controller is configured to:

store first data in the NAND array using a two-stage logical-to-physical (L2P) mapping table comprising a partition table and a plurality of table partitions;

store the partition table in the byte-rewritable non-volatile memory, the partition table comprising a plurality of indexes corresponding to the plurality of table partitions; and

store the plurality of table partitions in the block-erasable NVM, each table partition comprising a plurality of physical addresses of the NAND array mapped to logical addresses of the first data.

20. The SSD of claim 19 , wherein the controller is further configured to:

store second data in the NAND array;

update one or more of the plurality of table partitions to store one or more physical addresses of the NAND array for storing the second data; and

update one or more indexes of the partition table corresponding to the updated one or more table partitions.

21. The SSD of claim 19 , wherein the controller is further configured to:

cache one or more of the table partitions in the byte-rewritable non-volatile memory.

Assignments (10)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 4, 2018
From: MYRAN, MARK DAVID; MISHRA, CHANDAN; GHOLAMIPOUR, AMIR HOSSEIN; COMETTI, ALDO GIOVANNI; YOO, NAMHOON
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 045724/0783 →
Cited By (1)
US 12,321,278