Adaptive transaction layer packet for latency balancing
View Patent ↗Embodiments of the present disclosure generally relate to a storage device with reduced latency and a method of accessing data by a storage device with reduced latency. In one embodiment, a method of accessing data by a storage device with reduced latency include triggering a controller of the storage device for issuing a host read request. The controller determines if latency is critical for completion of the host read request. The controller issues the host read request in dynamic host read request size if latency is critical.
1. A method of accessing data by a storage device with reduced latency, comprising:
triggering a controller of the storage device for issuing a host read request;
determining if latency is critical for completion of the host read request; and
issuing the host read request in a dynamic host read request size if latency is critical, wherein the dynamic host read request size is lower than a static maximum read request size, wherein the host read request is part of a forced unit access write operation.
2. The method of claim 1 , wherein the host read request is fetching from a host command submission queue.
3. The method of claim 2 , wherein the host command submission queue has a low command queue depth.
4. The method of claim 1 , wherein the host read request is fetching from a host memory buffer.
5. The method of claim 4 , wherein the host read request is fetching an internal table from the host memory buffer.
6. A storage device with reduced latency, comprising:
a non-volatile memory;
a controller coupled to the non-volatile memory, the controller comprising:
physical layers (phys) adapted to be linked to a host;
a direct memory access module configured to execute data transfers between the host and the storage device without involvement from a CPU, the direct memory access module comprising:
an adaptive transaction layer packets (TLP) attributes selector, wherein the adaptive TLP attributes selector utilizes a latency table generated by a latency monitor to correlate a read request size to select based upon a measured latency; and
the latency monitor, the latency monitor configured to measure a plurality of latencies between a plurality of read request TLPs issued by the direct memory access module and a plurality of completion transaction layer packets received by the controller.
7. The storage device of claim 6 , wherein the phy is adapted to linked to the host using a PCI express protocol.
8. The storage device of claim 6 , wherein the controller further comprises a latency table storing measured latencies between the plurality of read request transaction layer packets and the plurality of completion transaction layer packets.
9. The storage device of claim 6 , wherein the controller further comprises a cache operable to store a latency table.
10. The storage device of claim 6 , wherein the controller further comprises a direct memory access module configured to issue a host read request in a transaction size based on the measured plurality of latencies.
11. The storage device of claim 10 , wherein the direct module access module determines whether the host read request is latency critical.
12. The storage device of claim 10 , wherein the direct memory access module selects the transaction size based upon a desired latency correlated to one of the measured plurality of latencies.
13. The storage device of claim 12 , wherein the selected transaction size does not exceed a maximum TLP payload size ceiling supported by the storage device, the host, and any devices coupling the storage device and the host.
14. A method of accessing data by a storage device with reduced latency, comprising:
determining whether a host read request to be issued is latency critical;
determining whether a transaction size to be requested by a host read request is greater than a maximum transaction layer packets (TLP) payload size;
selecting a read request size in response to determining the transaction size is greater than the maximum transaction layer packet payload size; and
issuing a host read request in the selected read request size, wherein the host read request is part of a forced unit access write operation.
15. The method of claim 14 , wherein the selected read request size is selected based upon a desired latency.
16. The method of claim 14 , wherein the selected read request size is selected by matching a measured latency of prior host request requests.
17. The method of claim 14 , wherein the selected read request size does not exceed a supported maximum TLP payload size ceiling of the storage device, of the host, and any other devices connecting the storage device and the host.
18. The method of claim 14 , wherein the selected read request size is less than a static maximum read request size.
19. The method of claim 14 , wherein the storage device and the host are linked through a PCI Express protocol.
20. A storage device with reduced latency, comprising:
a non-volatile memory;
a transaction layer packet (TLP) payload size selector means, the TLP payload size selector means configured to select a transaction size of a read request TLP based upon a desired latency; and
a direct memory access module configured to execute data transfers between a host and the storage device without involvement from a CPU, the direct memory access module comprising:
an adaptive TLP attributes selector, wherein the adaptive TLP attributes selector utilizes a latency table generated by a latency monitor to correlate a read request size to select based upon a measured latency.
21. The storage device of claim 20 , wherein the storage device is linked to a host over a PCI Express protocol.
22. The storage device of claim 20 , wherein the TLP payload size selector means is configured to access a latency table to select the transaction size.
23. The storage device of claim 20 , wherein the TLP payload size selector means selects the transaction size of the read request TLP based upon an attribute of the read request TLP.
24. The storage device of claim 23 , wherein the attribute of the read request TLP is whether the read request is latency critical.
25. A storage device with reduced latency, comprising:
a non-volatile memory; and
a controller coupled to the non-volatile memory and coupled to a host through one or more PCIe links, wherein the controller is operable to:
determine if latency is critical for completion of a host read request; and
issue the host read request in a selected read request size based upon a selected latency, wherein the host read request is part of a forced unit access write operation.
26. The storage device of claim 25 , wherein the host read request comprises one or more read request transaction layer packets (TLPs) with a path from the storage device to a switch to the host.
27. The storage device of claim 26 , wherein the switch is in a store-and-forward mode.
28. The storage device of claim 25 , wherein the host read request is fetching a host command from an NVMe command submission queue of a host memory space.
29. The storage device of claim 25 , wherein the host read request is fetching an address translation table from a host memory buffer.