IP Library Granted Patent US 11,314,418
Granted Patent B2
US 11,314,418 · App. 17/210,277 · Granted Apr 26, 2022

Extensible storage system and method

Inventors: Rajesh Koul (San Jose, CA); Rodney N. Mullendore (San Jose, CA); James J. Walsh (Santa Clara, CA)
Assignee: Western Digital Technologies, Inc.
G06F3/0613G06F3/0607G06F3/0659G06F3/0664G06F3/0683G06F3/0688G06F13/102G06F13/4045Y02D10/00
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Quick Facts
Patent No.
US 11,314,418
App. No.
17/210,277
Granted
Apr 26, 2022
Kind
B2
Abstract

A storage system controller chip includes routing circuitry comprising a host interface for coupling to a host device and an extension interface for coupling to a secondary controller chip. A host controller is coupled to a logical interface of the routing circuitry for receiving a host data access command from the host device via the host interface and logical interface. The routing circuitry transfers the host data access command to the secondary controller chip via the extension interface. The storage system controller chip further includes processor circuitry coupled to the logical interface of the routing circuitry. The processor circuitry receives an indication from the secondary controller chip via the extension interface that execution of the host data access command has been completed by the secondary controller chip and instructs the host controller to notify the host device that execution of the host data access command has been completed.

Claims (82)

1. A machine-implemented method for a data storage system comprising a first controller and one or more second controllers, the machine-implemented method comprising:

capturing a first command at the first controller using a first port of the first controller;

transmitting the first command from the first controller to a second controller coupled to the first controller using a second port of the first controller;

determining, by the first controller, whether the first controller is responsible for a first portion of data associated with the first command and whether the second controller is responsible for a second portion of the data associated with the first command;

executing, by the first controller, the first command for the first portion of the data; and

executing, by the second controller, the first command for the second portion of the data,

wherein:

the second controller is one of the one or more second controllers and is different from the first controller;

a bandwidth of the first port is split among the first controller and the one or more second controllers;

the bandwidth of the first port is higher than a bandwidth of the second port; and

the second controller skips determining whether the second controller is responsible for the second portion of the data.

2. The machine-implemented method of claim 1 , wherein each of the first controller and the second controller utilizes less than an entirety of the bandwidth of the first port.

3. The machine-implemented method of claim 1 , comprising:

transmitting the first command to the second controller in response to determining that the second controller is responsible for the second portion of the data; and

providing an indication that execution of the first command is completed in response to the second controller completing execution of the first command.

4. The machine-implemented method of claim 3 , wherein determining, whether the second controller is responsible for the second portion of the data associated with the first command, comprises:

determining a logical address of the data associated with the first command; and

comparing the logical address to a logical address range associated with the second controller,

wherein a logical address of the second portion of the data is within the logical address range, and

wherein the machine-implemented method comprises: altering the first command based on the logical address range, wherein the altered first command is transmitted to the second controller.

5. The machine-implemented method of claim 3 , wherein determining, whether the second controller is responsible for the second portion of the data associated with the first command, comprises:

determining a logical namespace of the data associated with the first command; and

comparing the logical namespace of the data with a logical name space associated with the second controller, and

wherein the logical namespace of the second portion of the data satisfies the logical name space associated with the second controller.

6. The machine-implemented method of claim 1 , wherein the first controller comprises an internal interface for receiving the first command or a second command for execution, and wherein the bandwidth of the first port is equal to or greater than a sum of a bandwidth of the internal interface and the bandwidth of the second port.

7. A data storage system, comprising:

a first controller and one or more second controllers,

wherein;

the first controller is configured to receive a first command using a first port of the first controller and configured to transmit the first command to a second controller using a second port of the first controller;

the second controller is one of the one or more second controllers and is different from the first controller;

a bandwidth of the first port is configured to be split among the first controller and the one or more second controllers;

the bandwidth of the first port is higher than a bandwidth of the second port;

the first controller is configured to determine whether the first controller is responsible for a first portion of data associated with the first command and whether the second controller is responsible for a second portion of the data associated with the first command;

the first controller is configured to execute the first command for the first portion of the data;

the second controller is configured to execute the first command for the second portion of the data; and

the second controller is configured to skip determining whether the second controller is responsible for the second portion of the data.

8. The data storage system of claim 7 , wherein each of the first controller and the second controller is configured to utilize less than an entirety of the bandwidth of the first port.

9. The data storage system of claim 7 , wherein the first controller is configured to cause:

transmitting the first command to the second controller in response to determining that the second controller is responsible for the second portion of the data; and

providing an indication that execution of the first command is completed in response to the second controller completing execution of the first command.

10. The data storage system of claim 9 , wherein determining, whether the second controller is responsible for the second portion of the data associated with the first command, comprises:

determining a logical address of the data associated with the first command; and

comparing the logical address to a logical address range associated with the second controller, and

wherein a logical address of the second portion of the data is within the logical address range.

11. The data storage system of claim 10 , wherein the first controller is configured to cause:

altering the first command based on the logical address range; and

transmitting the altered first command to the second controller.

12. The data storage system of claim 9 , wherein determining, whether the second controller is responsible for the second portion of the data associated with the first command, comprises:

determining a logical namespace of the data associated with the first command; and

comparing the logical namespace of the data with a logical name space associated with the second controller, and

wherein the logical namespace of the second portion of the data satisfies the logical name space associated with the second controller.

13. The data storage system of claim 9 , wherein the second controller is configured to cause:

receiving the first command using a first port of the second controller;

executing the first command for the second portion of the data; and

providing an indication that the first command is completed for the second portion of the data.

14. The data storage system of claim 7 , wherein the first controller comprises an internal interface configured to receive the first command or a second command for execution, and wherein the bandwidth of the first port is equal to or greater than a sum of a bandwidth of the internal interface and the bandwidth of the second port.

15. The data storage system of claim 7 , wherein the first controller is configured to cause:

receiving an indication that execution of the first command by the second controller is completed; and

providing a notification to a host in response to the received indication.

16. The data storage system of claim 7 , wherein:

the second controller comprises a configuration setting; and

the configuration setting of the second controller is configured to designate the second controller to skip the determining.

17. The data storage system of claim 7 , wherein:

each of the first controller and the second controller comprises registers;

the first controller is configured to assess one or more of the registers of the second controller;

the second controller is configured to assess one or more of the registers of the first controller; and

the second controller is configured to update a status of the first command in the first controller.

18. The data storage system of claim 7 , wherein:

the first controller is visible to a host that has provided the first command to the first controller; and

the second controller is invisible to the host.

19. An apparatus, comprising:

means for capturing a first command at a first controller using a first port of the first controller;

means for transmitting the first command from the first controller to a second controller coupled to the first controller using a second port of the first controller;

means for splitting a bandwidth of the first port among the first controller and one or more second controllers;

means for determining, at the first controller, whether the first controller is responsible for a first portion of data associated with the first command and whether the second controller is responsible for a second portion of the data associated with the first command;

means for executing, at the first controller, the first command for the first portion of the data;

means for executing, at the second controller, the first command for the second portion of the data; and

means for skipping determining, at the second controller, whether the second controller is responsible for the second portion of the data,

wherein;

the second controller is one of the one or more second controllers and is different from the first controller; and

the bandwidth of the first port is higher than a bandwidth of the second port.

20. The apparatus of claim 19 , wherein each of the first controller and the second controller is configured to utilize less than an entirety of the bandwidth of the first port.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 056285 FRAME 0292 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0001 →
SECURITY INTEREST Recorded May 19, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 056285/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2021
From: KOUL, RAJESH; MULLENDORE, RODNEY N.; WALSH, JAMES J.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 055974/0084 →