Flash dual inline memory modules with multiplexing support circuits
In one implementation, flash memory chips are provided with an operating power supply voltage to substantially match a power supply voltage expected at an edge connector of a dual inline memory module. The one or more of the flash memory chips and a memory support application integrated circuit (ASIC) may be mounted together into a multi-chip package for integrated circuits. The one or more flash memory chips and the memory support ASIC may be electrically coupled together by routing one or more conductors between each in the multi-chip package. The multi-chip package may be mounted onto a printed circuit board (PCB) of a flash memory DIMM to reduce the number of packages mounted thereto and reduce the height of the flash memory DIMM. The number of printed circuit board layers may also be reduced, such as by integrating address functions into the memory support ASIC.
1. A flash memory dual inline memory module (DIMM) comprising:
a printed circuit board with an edge connector;
a plurality of data support application specific integrated circuits (ASICs) coupled to the edge connector, the plurality of data support ASICs including a multiplexer/demultiplexer to respectively multiplex and demultiplex data between a first data bus of a first bit width and a second data bus of a second bit width differing from the first bit width;
a first plurality of flash memory parts coupled to the plurality of data support ASICs, the first plurality of flash memory parts including one or more randomly accessible flash memory die to periodically store data in a non-volatile manner; and
a first address support ASIC coupled to the edge connector and the first plurality of flash memory parts.
2. The flash memory DIMM of claim 1 , wherein
the first address support ASIC to receive an encoded address from the edge connector to decode the encoded address and address one or more of the first plurality of flash memory parts and flash memory locations therein.
3. The flash memory DIMM of claim 1 , further comprising:
a second plurality of flash memory parts mounted to the printed circuit board in a second row parallel to the first row and electrically coupled to the plurality of data support ASICs and the address support ASICs, the second plurality of flash memory parts including one or more randomly accessible flash memory die to periodically store data in a non-volatile manner.
4. The flash memory DIMM of claim 3 , wherein
the first plurality of flash memory parts includes a first left plurality of flash memory parts and a first right plurality of flash memory parts in the first row;
the second plurality of flash memory parts includes a second left plurality of flash memory parts and a second right plurality of flash memory parts in the second row; and
the first address support ASIC is between the first left and first right plurality of flash memory parts to drive a first left and a first right plurality of address lines respectively thereto and between the second left and second right plurality of flash memory parts to drive a second left and a second right plurality of address lines respectively thereto.
5. The flash memory DIMM of claim 1 , wherein
each of the one or more randomly accessible flash memory die in the first plurality of flash memory parts and the data support ASIC to which they are coupled, are respectively mounted together into a first plurality of multi-chip packages and to a front side of the printed circuit board;
the first address support ASIC is mounted to the front side of the printed circuit board;
the first plurality of data support ASICs couple to a first plurality of pins of the edge connector on the front side of the printed circuit board; and
the flash memory DIMM further includes
a second plurality of data support application specific integrated circuits (ASICs) coupled to a second plurality of pins of the edge connector on the back side of the printed circuit board, the second plurality of data support ASICs to multiplex and demultiplex data between a first data bus of a first bit width and a second data bus of a second bit width differing from the first bit width;
a second plurality of flash memory parts coupled to the second plurality of data support ASICs and a second address support ASIC, the second plurality of flash memory parts including one or more randomly accessible flash memory die to periodically store data in a non-volatile manner;
the second address support ASIC coupled to the edge connector, the second plurality of flash memory parts, and the second plurality of data support ASICs; and
wherein each of the one or more randomly accessible flash memory die in the second plurality of flash memory parts and the data support ASIC to which they are coupled, are respectively mounted together into a second plurality of multi-chip packages and to a back side of the printed circuit board, and
the second address support ASIC is mounted to the back side of the printed circuit board.
6. The flash memory DIMM of claim 1 , wherein
each of the plurality of data support ASICs further include a data buffer to buffer data between the first data bus and the second data bus to emolliate signal timing differences between the first data bus and the second data bus.