Non-volatile storage system with adaptive command processing
An apparatus includes a plurality of memory die and a controller coupled to the plurality of memory die. The controller is configured to selectively process a plurality of random read commands in such a way to reduce a total time required to execute the random read commands.
1. An apparatus, comprising:
a plurality of memory die; and
a controller coupled to the plurality of memory die, the controller configured to selectively process a plurality of random read commands to reduce a total time required to execute the random read commands,
wherein the controller is configured to selectively process the plurality of random read commands by forming a plurality of read sets, each read set comprising a single random read command per memory die.
2. The apparatus of claim 1 , wherein the controller is configured to selectively process the plurality of random read commands based on a time required by the plurality of memory die to perform read-sense operations.
3. The apparatus of claim 1 , wherein the controller is configured to selectively process the plurality of random read commands by forming a plurality of read sets, each read set including no more than one random read command per memory die.
4. The apparatus of claim 1 , wherein the controller is configured to selectively process the plurality of random read commands by forming a plurality of read sets, each read set skipping random read commands that would result in multiple sense operations for a same memory die.
5. The apparatus of claim 1 , wherein the controller is configured to selectively process the plurality of random read commands by:
forming a first read set that includes no more than one random read command per memory die;
skipping a random read command that would result in multiple sense operations for a same memory die; and
including the skipped random read command in a subsequent read set.
6. The apparatus of claim 1 , wherein the controller comprises a single processor.
7. The apparatus of claim 1 , wherein the controller is coupled to the plurality of memory die via a shared command pipeline.
8. The apparatus of claim 1 , wherein the controller comprises no hardware automation.
9. The apparatus of claim 1 , wherein the controller is separate from and coupled to the plurality of memory die, and is configured to receive the plurality of random read commands from a host.
10. A method, comprising:
receiving random read commands at a memory device from a host, the memory device comprising a plurality of memory die;
adaptively processing the random read commands at the memory device to increase a number of random input-output operations per second processed by the memory device; and
adaptively processing the plurality of random read commands by forming a plurality of read sets, each read set comprising a single random read command per memory die.
11. The method of claim 10 , further comprising adaptively processing the plurality of random read commands based on a time required by the plurality of memory die to perform read-sense operations.
12. The method of claim 10 , further comprising adaptively processing the plurality of random read commands by forming a plurality of read sets, each read set including no more than one random read command per memory die.
13. The method of claim 10 , further comprising adaptively processing the plurality of random read commands by forming a plurality of read sets, each read set skipping random read commands that would result in multiple sense operations for a same memory die.
14. The method of claim 10 , comprising using a single processor to adaptively process the plurality of random read commands.
15. The method of claim 10 , wherein the plurality of memory die receive the plurality of random read commands via a shared command pipeline.
16. The method of claim 10 , comprising using no hardware automation to adaptively process the plurality of random read commands.
17. A system, comprising:
a memory device comprising a plurality of memory die; and
a controller coupled to the plurality of memory die, the controller configured to receive random read commands from a host, the controller comprising means for iteratively forming and executing a plurality of read sets, the plurality of read sets comprising a first read set and a current read set, the first read set comprising a single random read command per memory die and skipping a random read command that would result in multiple sense operations for a same memory die, the current read set including the skipped random read command.
18. The system of claim 17 , wherein the controller comprises a single processor coupled to the plurality of memory die via a shared command pipeline, and comprises no hardware automation.