IP Library Granted Patent US 10,726,865
Granted Patent B2
US 10,726,865 · App. 16/157,796 · Granted Jul 28, 2020

Zoned block command to stream command translator

Inventors: Darin Edward Gerhart (Oronoco, MN); Nicholas Edward Ortmeier (Rochester, MN); Cory Lappi (Rochester, MN); William Jared Walker (Rochester, MN)
Assignee: Western Digital Technologies, Inc.
G11B5/09G11B5/012
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Quick Facts
Patent No.
US 10,726,865
App. No.
16/157,796
Granted
Jul 28, 2020
Kind
B2
Abstract

A method for performing an operation of a memory arrangement, comprising receiving a command at a layer of a computer system, determining if the command received is one of a first command type or a second command type, determining a type of command that is able to be received and is capable of operation of the memory arrangement, comparing the type of command capable of operation of the memory arrangement and the received command at the layer, and converting the command received at the layer to a command type capable of operation of the memory arrangement when the type of command received at the layer is different than type of command that is able to be received and is capable of operation of the memory arrangement.

Claims (34)

1. A method for performing an operation of a memory arrangement, comprising:

receiving a command at a layer of a computer system;

determining if the command received is one of a first command type or a second command type;

determining a type of command that is able to be received and is capable of operation in the memory arrangement;

comparing the type of command capable of operation in the memory arrangement and the received command at the layer of the computer system; and

converting the command received at the layer to a command type capable of operation of the memory arrangement when the type of command received at the layer is different than type of command that is able to be received and is capable of operation in the memory arrangement, wherein the converting comprises converting a zone block command to a stream command.

2. The method according to claim 1 , wherein the layer of the computer system is within a host system.

3. The method according to claim 1 , wherein the layer of the computer system is within an SAS expander.

4. The method according to claim 1 , wherein the layer of the computer system is in the memory arrangement.

5. The method according to claim 1 , wherein the first type is a stream type command.

6. The method according to claim 1 , wherein the first type is a zoned block command.

7. The method according to claim 1 , wherein the memory arrangement is a solid state drive.

8. The method according to claim 1 , further comprising:

transmitting the command type capable of operation for the memory arrangement to the memory arrangement.

9. The method according to claim 1 , further comprising:

receiving the command type capable of operation for the memory arrangement at the memory arrangement.

10. A method of creating an optimal interface for a memory arrangement, comprising:

connecting the memory arrangement to a host system;

querying the memory arrangement as to a type of command that will be accepted and operated upon by the memory arrangement; and

preparing an interface between the host system and memory arrangement such that commands provided by the host system will be accepted and operated upon by the memory arrangement, wherein the accepted and operated comprises converting a zone block command to a stream command.

11. The method of claim 10 , wherein the interface between the host system and the memory arrangement provides at least one of data and commands from the memory such that the host system will be capable of accepting the data and acting upon the commands from the memory.

12. The method according to claim 10 , wherein the querying the memory arrangement as to the type of command that will be accepted and operated upon by the memory arrangement detects one of a stream compliant device and a zoned block compliant device.

13. The method according to claim 12 , wherein the stream compliant device is a solid state drive.

14. The method according to claim 12 , wherein the zoned block compliant device is a hard disk drive.

15. The method according to claim 12 , wherein an abstraction layer presents the interface of the memory arrangement to the host system as a device compliant for memory storage with the host system.

16. A method for performing an operation of a memory arrangement, comprising:

receiving a command at a layer of a computer system;

determining if the command at the layer of the computer system corresponds to a virtual zoned block device; and

independently processing the command at the layer of the computer system when the command at the layer of the computer system corresponds to the virtual zoned block device, wherein the processing comprises converting a zone block command to a stream command.

17. The method according to claim 16 , wherein the independently processing the command occurs in a component of a memory arrangement.

18. The method according to claim 17 , wherein the component is a Z stream translator.

19. The method according to claim 16 , wherein the memory arrangement is a solid state drive.

20. The method according to claim 16 , further comprising:

transmitting the command to the memory arrangement.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 12, 2018
From: GERHART, DARIN EDWARD; ORTMEIER, NICHOLAS EDWARD; LAPPI, CORY; WALKER, WILLIAM JARED
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 047147/0516 →
Cited By (6)
US 12,292,827 US 12,298,902 US 12,360,892 US 12,504,899 US 12,572,468 US 12,625,639