IP Library Granted Patent US 10,489,077
Granted Patent B2
US 10,489,077 · App. 15/607,521 · Granted Nov 26, 2019

Systems and methods for controlling metapage storage on data storage devices

Inventors: Sourabh Sankule (Bangalore, IN); Avinash Sharma (Bangalore, IN); Mikhail Palityka (Oakville, CA)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G06F3/064G06F3/061G06F3/0679G06F12/0246G06F13/1694G06F2212/1041G06F2212/7201G06F2212/7206G06F2212/7208
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Quick Facts
Patent No.
US 10,489,077
App. No.
15/607,521
Granted
Nov 26, 2019
Kind
B2
Abstract

Systems and methods are disclosed for executing access commands for a data storage device. A data storage device receives first data to be written to a plurality of dies/non-volatile memory arrays. The data storage device transfers a first metapage of the first data to the plurality of dies/non-volatile memory arrays. The data storage device also programs the first metapage to a first metablock of the plurality of dies and programs the first metapage to a second metablock of the plurality of dies/non-volatile memory arrays. The data storage device further transfers a second metapage to the plurality of dies/non-volatile memory arrays. Programming the first metapage to the first metablock may be simultaneous with transferring the second metapage to the plurality of dies/non-volatile memory arrays.

Claims (64)

1. A data storage device, comprising:

a non-volatile solid-state memory comprising a plurality of dies; and

a controller coupled to the plurality of dies via a channel, the controller configured to:

receive first data to be written to the plurality of dies;

transfer a first metapage of the first data to the plurality of dies;

program the first metapage to a first metablock of the plurality of dies;

program the first metapage to a second metablock of the plurality of dies; and

transfer a second metapage to the plurality of dies and program the second metapage to a third metablock of the plurality of dies, wherein programming the first metapage to the first metablock is simultaneous with transferring the second metapage to the plurality of dies and wherein programming the first metapage to the second metablock of the plurality of dies is simultaneous with programming the second metapage to the third metablock of the plurality of dies.

2. The data storage device of claim 1 , wherein programming a portion of the first metapage to the first metablock is further simultaneous with programming another portion of the first metapage to the second metablock.

3. The data storage device of claim 1 , wherein the controller is further configured to:

identify a first set of blocks from the plurality of dies as the first metablock; and

identify a second set of blocks from the plurality of dies as the second metablock.

4. The data storage device of claim 3 , wherein each of the first set of blocks and the second set of blocks comprises at least one block from each of the plurality of dies.

5. The data storage device of claim 1 , wherein the controller is further configured to:

check whether an error occurred when programming the first metapage to the first metablock.

6. The data storage device of claim 5 , wherein the controller is further configured to:

erase the second metablock in response to determining that no error occurred when programming the first metapage to the first metablock.

7. The data storage device of claim 5 , wherein the controller is further configured to:

erase the first metablock in response to determining that the error occurred when programming the first metapage to the first metablock.

8. The data storage device of claim 1 , wherein the plurality of dies comprises single-level cell (SLC) memory.

9. The data storage device of claim 8 , further comprising a second plurality of dies, wherein the second plurality of dies comprises multi-level cell (MLC) memory.

10. The data storage device of claim 9 , wherein the MLC memory comprise triple-level cell (TLC) memory.

11. The data storage device of claim 9 , wherein the controller is further configured to:

move a set of blocks from the SLC memory to the MLC memory.

12. The data storage device of claim 11 , wherein moving the set of blocks from the SLC memory to the MLC memory is simultaneous with programming the first metapage to the first metablock.

13. The data storage device of claim 1 , wherein the first data is received via a first write command received from a host and wherein the second metapage is from the first data.

14. The data storage device of claim 1 , wherein the second metapage is from a second data received via a second write command received from a host.

15. A method comprising:

receiving first data to be written to a plurality of non-volatile memory arrays of a data storage device;

transferring a first metapage of the first data to the plurality of non-volatile memory arrays;

writing the first metapage to a first metablock of the plurality of non-volatile memory arrays;

writing the first metapage to a second metablock of the plurality of non-volatile memory arrays; and

transferring a second metapage to the plurality of non-volatile memory arrays and writing the second metapage to a third metablock of the plurality of dies, wherein writing the first metapage to the first metablock is simultaneous with transferring the second metapage to the plurality of non-volatile memory arrays and wherein writing the first metapage to the second metablock of the plurality of dies is simultaneous with writing the second metapage to the third metablock of the plurality of dies.

16. The method of claim 15 , wherein writing a portion of the first metapage to the first metablock is further simultaneous with writing another portion of the first metapage to the second metablock.

17. The method of claim 15 , further comprising:

identifying a first set of blocks from the plurality of non-volatile memory arrays as the first metablock; and

identifying a second set of blocks from the plurality of non-volatile memory arrays as the second metablock.

18. The method of claim 17 , wherein each of the first set of blocks and the second set of blocks comprises at least one block from each of the plurality of non-volatile memory arrays.

19. The method of claim 15 , further comprising:

checking whether an error occurred when writing the first metapage to the first metablock.

20. The method of claim 19 , further comprising:

erasing the second metablock in response to determining that no error occurred when writing the first metapage to the first metablock.

21. The method of claim 19 , further comprising:

erasing the first metablock in response to determining that the error occurred when writing the first metapage to the first metablock.

22. The method of claim 15 , wherein the plurality of non-volatile memory arrays comprises single-level cell (SLC) memory.

23. The method of claim 22 , wherein the data storage device further comprises a second plurality of non-volatile memory arrays and wherein the second plurality of non-volatile memory arrays comprises multi-level cell (MLC) memory.

24. The method of claim 15 , further comprising:

moving a set of blocks from the SLC memory to the MLC memory.

25. The method of claim 24 , wherein moving the set of blocks from the SLC memory to the MLC memory is simultaneous with programming the first metapage to the first metablock.

26. A data storage apparatus, comprising:

a plurality of dies; and

means for receiving first data to be written to the plurality of dies;

means for transferring a first metapage of the first data to the plurality of dies;

means for programing the first metapage to a first metablock of the plurality of dies;

means for programming the first metapage to a second metablock of the plurality of dies;

means for transferring a second metapage to the plurality of dies;

means for programming the second metapage to a third metablock of the plurality of dies;

means for controlling the means for programming the first metapage to the first metablock and the means for transferring the second metapage to the plurality of dies to program the first metapage to the first metablock and transfer the second metapage to the plurality of dies at the same time; and

means for controlling the means for programming the first metapage to the second metablock of the plurality of dies and the means for programming the second metapage to the third metablock of the plurality of dies to program the first metapage to the second metablock and program the second metapage to the third metablock at the same time.

27. The data storage apparatus of claim 26 , further comprising means for controlling the means for programming the first metapage to the first metablock and the means for programming the first metapage to the second metablock to program a portion of the first metapage to the first metablock and program another portion of the first metapage to the second metablock at the same time.

28. The data storage device of claim 26 , further comprising:

means for checking whether an error occurred when programming the first metapage to the first metablock;

means for erasing the second metablock in response to determining that no error occurred when programming the first metapage to the first metablock; and

means for erasing the first metablock in response to determining that the error occurred when programming the first metapage to the first metablock.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 28, 2017
From: SANKULE, SOURABH; SHARMA, AVINASH; PALITYKA, MIKHAIL
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 043731/0899 →
Continuity (1)
Related Publication 20180341406A1 · Nov 29, 2018