Multiple function level reset management
The controller is configured to receive commands from a host device through a PCIe bus having a MAC, send data to the host device through the PCIe bus, and execute a function level reset (FLR) command. The controller includes a direct memory access (DMA) unit and either a drain unit or a drain and drop unit coupled between the DMA and the PCIe bus. The units are configured to prevent transactions associated with the FLR command to pass from the DMA to the MAC during execution of the FLR command, where the preventing transactions comprises receiving a request from the DMA, storing the request in a pipe, removing the request from the pipe, and providing a response to the DMA without delivering the request to the MAC. The drain and drop unit is configured to drop a MAC generated response.
1. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
receive commands from a host device through a PCIe bus having a multiplier-accumulator (MAC);
send data to the host device through the PCIe bus; and
execute a function level reset (FLR) command, wherein the controller comprises a direct memory access (DMA) unit and a drain unit, wherein the drain unit is coupled between the DMA and the PCIe bus, and wherein the drain unit is configured to prevent transactions associated with the FLR command to pass from the DMA to the MAC during execution of the FLR command, and wherein the preventing transactions comprises receiving a request from the DMA, storing the request in a pipe, removing the request from the pipe, and providing a response to the DMA without delivering the request to the MAC.
2. The data storage device of claim 1 , wherein the drain unit is configured to permit transactions not associated with the FLR command to pass from the DMA to the MAC during execution of the FLR command.
3. The data storage device of claim 1 , wherein the drain unit is configured to store the prevented transactions in a transaction history buffer.
4. The data storage device of claim 1 , wherein the drain unit is configured to generate responses for the prevented transactions.
5. The data storage device of claim 4 , wherein the responses are delivered to the DMA without delivering the request to the MAC.
6. The data storage device of claim 1 , wherein the controller further comprises:
an encoder/decoder;
an error correction module; and
a flash interface module (FIM), wherein the encoder/decoder, error correction module, FIM, and DMA are all disposed along a data path in the controller.
7. The data storage device of claim 6 , wherein the controller further comprises a processor, wherein the processor is disposed along a control path and is coupled to the PCIe bus.
8. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
receive commands from a host device through a PCIe bus having a multiplier-accumulator (MAC);
send data to the host device through the PCIe bus; and
execute a function level reset (FLR) command, wherein the controller comprises a direct memory access (DMA) unit and a drain and drop unit, wherein the drain and drop unit is coupled between the DMA and the PCIe bus, and wherein the drain and drop unit is configured to:
receive a request from the DMA;
store the request in a pipe;
remove the request from the pipe; and
provide a response to the DMA, wherein the response is provided to the DMA without delivering the request to the MAC; and
drop a MAC generated response.
9. The data storage device of claim 8 , wherein the controller is further configured to determine whether the request is subject to the FLR command.
10. The data storage device of claim 8 , wherein the controller is further configured to pass the request to the PCIe bus upon determining that the request is not subject to the FLR command.
11. The data storage device of claim 8 , wherein the controller is further configured to receive a response from the PCIe bus, determine that the response is not subject to the FLR command, and provide the response to the DMA.
12. The data storage device of claim 8 , wherein the controller is further configured to receive a response from the PCIe bus and determine that the response is subject to the FLR command.
13. The data storage device of claim 8 , wherein the controller is further configured to determine that the pipe is not empty, determine that a head of the pipe is subject to the FLR command, and remove the request from the pipe.
14. The data storage device of claim 13 , wherein the controller is further configured to provide a response to the DMA upon determining that the head of the pipe is subject to the FLR command.
15. The data storage device of claim 8 , wherein the controller is further configured to determine that the pipe is not empty and determine that a head of the pipe is not subject to the FLR command.
16. A data storage device, comprising:
means for storing data; and
a controller coupled to the means for storing data, wherein the controller is configured to:
receive commands to access the means for storing data from a host device through a PCIe bus having a multiplier-accumulator (MAC);
send data to the host device through the PCIe bus; and
provide a unique identifier to each command upon receipt, wherein the controller comprises a direct memory access (DMA) unit and a drain unit, wherein the drain unit is coupled between the DMA and the PCIe bus, and wherein the drain unit is configured to prevent transactions having the unique identifier to pass from the DMA to the MAC.
17. The data storage device of claim 16 , wherein the unique identifier indicates the command should not access an interface to a host device.
18. The data storage device of claim 16 , wherein the controller is further configured to provide an error indication to firmware indicating commands with the unique identifier were consumed in the drain.
19. The data storage device of claim 16 , wherein the drain unit is configured to permit commands that do not have the unique identifier to pass from the DMA to the MAC.
20. The data storage device of claim 16 , wherein the unique identifier is utilized throughout a lifespan of the command to which the unique identifier is provided.