DRAM-less SSD with secure HMB for low latency
Aspects of the present disclosure generally relate to data storage devices and related methods that use secure host memory buffers and low latency operations. In one aspect, a controller is configured to fetch a command from a host device, and fetch entry data from a host memory buffer (HMB) of the host device in response to the command from the host device. The HMB is utilized in place of DRAM in the controller so that the data storage device is DRAM-less. In one embodiment, the entry data includes a logical to physical (L2P) address. The controller is also configured to fetch read data from the one or more memory devices using the entry data, conduct a validity check of the entry data fetched from the HMB simultaneously with the fetching of the read data from the one or more memory devices, and transmit validity result data to the host device.
1. A data storage device, comprising:
one or more memory devices; and
a controller coupled to the one or more memory devices, wherein the controller is DRAM-less, and wherein the controller is configured to:
fetch a command from a host device, wherein the host device comprises a host memory buffer (HMB);
fetch entry data from the HMB in response to the command from the host device;
fetch read data from the one or more memory devices using the entry data and conduct a validity check of the entry data fetched from the HMB, wherein the fetching read data from the one or more memory devices and the conducting a validity check occurs simultaneously; and
transmit validity result data to the host device.
2. The data storage device of claim 1 , wherein the one or more memory devices are one or more NAND devices.
3. A data storage device, comprising:
one or more memory devices; and
a controller coupled to the one or more memory devices, wherein the controller is DRAM-less, and wherein the controller is configured to:
fetch a command from a host device, wherein the host device comprises a host memory buffer (HMB);
fetch entry data from the HMB in response to the command from the host device;
fetch read data from the one or more memory devices using the entry data;
conduct a validity check of the entry data fetched from the HMB simultaneously with the fetching of the read data from the one or more memory devices; and
transmit validity result data to the host device, wherein the HMB comprises a Merkle tree having a plurality of hashes, and the validity check comprises:
comparing a signature of a top level hash of the plurality of hashes to a stored signature that is stored within the controller; and
determining if the signature is the same as or different from the stored signature.
4. The data storage device of claim 3 , wherein the validity result data transmitted to the host device comprises the read data if the signature is the same as the stored signature.
5. The data storage device of claim 3 , wherein the validity result data transmitted to the host device comprises garbage data if the signature is different from the stored signature.
6. The data storage device of claim 3 , wherein the controller is further configured to post a completion message to the host device.
7. The data storage device of claim 6 , wherein the completion message comprises a valid notification if the signature is the same as the stored signature.
8. The data storage device of claim 6 , wherein the completion message comprises an error notification if the signature is different from the stored signature.
9. The data storage device of claim 3 , wherein the fetching the read data from the one or more memory devices comprises sending a sense request to the one or more memory devices prior to the determining if the signature is the same as or different from the stored signature.
10. A data storage device, comprising:
one or more memory devices; and
a controller coupled to the one or more memory devices, wherein the controller is DRAM-less, and wherein the controller is configured to:
fetch a command from a host device, wherein the host device comprises a host memory buffer (HMB), and the HMB comprises a Merkle tree having a plurality of hashes;
fetch entry data from the HMB in response to the command from the host device;
fetch read data from the one or more memory devices using the entry data; and
conduct a validity check of the entry data fetched from the HMB simultaneously with the fetching of the read data from the one or more memory devices, the validity check comprising:
comparing a signature of a top level hash of the plurality of hashes to a stored signature that is stored within the controller, and
determining if the signature is the same as or different from the stored signature.
11. The data storage device of claim 10 , wherein the controller comprises:
a control path comprising one or more processors, wherein the control path is configured to control the one or more memory devices;
a host interface module, wherein the host interface module is configured to communicate with the host device and the control path, and the host interface module is configured to manage the HMB;
a direct memory access (DMA), wherein the DMA is configured to communicate with the host interface module and the control path;
an error correction code (ECC), wherein the ECC is configured to communicate with the DMA and configured to encode and decode data for error correction; and
a flash interface module, wherein the flash interface module is configured to communicate with the one or more memory devices.
12. The data storage device of claim 11 , wherein the fetching the read data from the one or more memory devices comprises the control path sending a sense request to the one or more memory devices.
13. The data storage device of claim 11 , wherein the host interface module executes the validity check.
14. The data storage device of claim 11 , wherein the DMA is configured to send instructions to the host interface module to transmit validity result data to the host device.
15. The data storage device of claim 14 , wherein the DMA is further configured to send instructions to the host interface module to post a completion message to the host device.
16. A data storage device, comprising:
memory means; and
a controller coupled to the memory means, wherein the controller is DRAM-less, and wherein the controller is configured to:
fetch a command from a host device, wherein the host device comprises a host memory buffer (HMB);
fetch entry data from the HMB in response to the command from the host device;
fetch read data from one or more memory devices using the entry data and conduct a validity check of the entry data fetched from the HMB, wherein the fetching read data from the one or more memory devices and the conducting a validity check occurs simultaneously; and
transmit validity result data to the host device.
17. The data storage device of claim 16 , wherein the controller includes a host interface module coupled to a direct memory access (DMA).
18. The data storage device of claim 17 , wherein the DMA is coupled to an error correction module and a flash interface module (FIM).
19. The data storage device of claim 17 , wherein conducting the validity check and fetching read data is performed simultaneously.
20. A data storage device, comprising:
memory means; and
a controller coupled to the memory means, wherein the controller is DRAM-less, and wherein the controller is configured to:
fetch a command from a host device, wherein the host device comprises a host memory buffer (HMB);
fetch entry data from the HMB in response to the command from the host device;
fetch read data from one or more memory devices using the entry data;
conduct a validity check of the entry data fetched from the HMB simultaneously with the fetching of the read data from the one or more memory devices; and
transmit validity result data to the host device, wherein conducting the validity check of the entry data comprises:
comparing a signature of a top level hash of a plurality of hashes stored in a Merkle tree of the HMB to a stored signature; and
determining if the signature is the same as or different from the stored signature.