Manufacturing process for separating logic and memory array
View Patent ↗A semiconductor device is disclosed including an integrated memory module. The integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated flash memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the second die may be flip-chip bonded to the first die. The flip-chip bond pads on the first and second dies may be made small, with a small pitch, to allow a large number of electrical interconnections between the first and second semiconductor dies.
1. An integrated memory module comprising:
a first semiconductor die comprising at least a first group of bond pads;
a second semiconductor die comprising a second group of bond pads bonded to the at least first group of bond pads of the first semiconductor die to electrically and physically couple the second semiconductor die to the first semiconductor die;
wherein the first and second coupled semiconductor dies together are configured as an integrated flash memory.
2. The integrated memory module of claim 1 , wherein the first semiconductor die comprises a plurality of memory cells.
3. The integrated memory module of claim 2 , wherein the second semiconductor die comprises a control circuit for controlling access to the plurality of memory cells.
4. The integrated memory module of claim 3 , wherein the control circuit comprises a complementary metal-oxide-semiconductor integrated circuit.
5. The integrated memory module of claim 1 , further comprising a third group of bond pads on the first semiconductor die configured to receive electrical connectors for electrically connecting the integrated memory module to a host device.
6. The integrated memory module of claim 5 , wherein the third group of bond pads on the first semiconductor die are configured to receive wire bonds for electrically connecting the integrated memory module to the host device.
7. An integrated memory module comprising:
a first semiconductor die comprising:
a plurality of memory cells,
a first group of bond pads electrically coupled to the plurality of memory cells;
a second semiconductor comprising:
control circuits for controlling access to the plurality of memory cells on the first semiconductor die, and
a second group of bond pads bonded the first group of bond pads of the first semiconductor die to electrically couple the second semiconductor die to the first semiconductor die;
wherein the first and second coupled semiconductor dies together are configured as an integrated flash memory.
8. The integrated memory module of claim 7 , wherein the number of bond pads in the second group coupled to the bond pads in the first group comprise between 100 and 1,000.
9. The integrated memory module of claim 7 , wherein the number of bond pads in the second group coupled to the bond pads in the first group comprise between 10,000 and 100,000.
10. The integrated memory module of claim 7 , wherein the control circuits comprises a complementary metal-oxide-semiconductor integrated circuit.
11. The integrated memory module of claim 7 , further comprising a third group of bond pads on the first semiconductor die configured to receive electrical connectors for electrically connecting the integrated memory module to a host device.
12. The integrated memory module of claim 11 , wherein the third group of bond pads on the first semiconductor die are configured to receive wire bonds for electrically connecting the integrated memory module to the host device.
13. An integrated memory module comprising:
a first semiconductor die comprising first bond pad means for electrically connecting the first semiconductor die;
a second semiconductor die comprising second bond pads means for bonding to the first bond pad means;
wherein the first and second coupled semiconductor dies together are configured as an integrated flash memory.
14. The integrated memory module of claim 13 , wherein the first semiconductor die comprises a plurality of memory cells.
15. The integrated memory module of claim 14 , wherein the second semiconductor die comprises a control circuit for controlling access to the plurality of memory cells.
16. The integrated memory module of claim 15 , wherein the control circuit comprises a complementary metal-oxide-semiconductor integrated circuit.
17. The integrated memory module of claim 13 , further comprising third bond pad means on the first semiconductor die for receiving electrical connectors to electrically connect the integrated memory module to a host device.
18. The integrated memory module of claim 17 , wherein the third bond pad means on the first semiconductor die are configured to receive wire bonds for electrically connecting the integrated memory module to the host device.