IP Library Granted Patent US 12,432,055
Granted Patent B2
US 12,432,055 · App. 17/732,943 · Granted Sep 30, 2025

Low latency block cipher in memory devices

Inventors: Yan Dumchin (Beer Sheva, IL); Tzvi Alon (Jerusalem, IL); Yuval Yoskovits (Tel Aviv, IL)
Assignee: Sandisk Technologies, Inc.
H04L9/0891H04L9/0618H04L9/0861
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Quick Facts
Patent No.
US 12,432,055
App. No.
17/732,943
Granted
Sep 30, 2025
Kind
B2
Abstract

A storage device includes multiple memory dies and a controller configured to: (i) encrypt a data block using a key schedule that includes a plurality of round keys generated from an encryption key, the encrypting resulting in an encrypted data block; (ii) during the encrypting, modify a key register during a first plurality of iterations, the key register being updated to a final state of the key register after a final iteration of the plurality of iterations; (iii) store the final state of the key register as a decryption key; and (iv) decrypt the encrypted data block using another key schedule that includes the plurality of round keys that are generated using the decryption key during a second plurality of iterations.

Claims (104)

1. A method, comprising:

encrypting a data block using a first key schedule that includes a plurality of round keys generated from an encryption key, the encrypting resulting in an encrypted data block;

during the encrypting, modifying a key register during a first plurality of iterations, the key register being updated to a final state after a final iteration of the plurality of iterations, and wherein modifying the key register for each of the first plurality of iterations comprises:

cyclically rotating bits of the key register a predetermined number of positions;

performing a non-linear substitution operation on a first predetermined number of bits in a first set of predetermined bit positions of the key register; and

performing an exclusive-or (XOR) operation between (i) a second predetermined number of bits in a second set of predetermined bit positions of the key register and (ii) a value of a round counter for the first plurality of iterations;

storing the final state of the key register as a decryption key; and

decrypting the encrypted data block using a second key schedule that includes the plurality of round keys that are generated using the decryption key during a second plurality of iterations.

2. The method of claim 1 , wherein decrypting the encrypted data block further comprises:

storing the decryption key into the key register;

initiating the second plurality of iterations starting at a last iteration value and decreasing to a first iteration value; and

during each iteration of the second plurality of iterations:

updating the key register based, at least in part, on a current iteration value; and

generating a round key from the key register using a first number of most significant bits of the key register.

3. The method of claim 2 , wherein decrypting the encrypted data block further comprises:

storing the encrypted data block in a data register; and

during each iteration of the second plurality of iterations:

applying the generated round key to the data register by performing an exclusive-or (XOR) operation on the data register using the generated round key.

4. The method of claim 2 , wherein updating the key register based, at least in part, on the current iteration value further comprises:

performing an exclusive-or (XOR) operation between (i) a first predetermined number of bits in a first set of predetermined bit positions of the key register and (ii) a value of a round counter for the second plurality of iterations;

performing an inverse non-linear substitution operation on a second predetermined number of bits in a second set of predetermined bit positions of the key register; and

cyclically rotating bits of the key register a predetermined number of bit positions in a predetermined direction.

5. The method of claim 1 , wherein cyclically rotating bits of the key register a predetermined number of positions comprises cyclically rotating the bits of the key register the predetermined number of bit positions in a predetermined direction.

6. The method of claim 1 , further comprising:

during each iteration of the first plurality of iterations:

performing an encrypting operation using a round counter previously generated from the key register; and

in parallel with the performing of the encryption, generating a next round counter using the key register, the next round counter to be used during a next iteration.

7. The method of claim 1 , further comprising, during the encrypting:

storing the encryption key into the key register;

generating a first round key;

initiating the first plurality of iterations starting at a first iteration value and increasing to a last iteration value; and

during each iteration of the first plurality of iterations:

performing an encrypting operation using a round counter previously generated; and

in parallel with the performing of the encryption, generating a next round counter using the key register to be used during a next iteration.

8. A storage device, comprising:

a non-volatile storage device comprising a plurality of memory dies, the non-volatile storage device including a plurality of memory cells; and

a controller communicatively coupled to the non-volatile storage device and configured to:

encrypt a data block using a first key schedule that includes a plurality of round keys generated from an encryption key, the encrypting resulting in an encrypted data block;

during the encrypting, modify a key register during a first plurality of iterations, the key register being updated to a final state after a final iteration of the plurality of iterations and wherein modifying the key register during each of the first plurality of iterations comprises:

cyclically rotating bits of the key register a predetermined number of positions;

performing a non-linear substitution operation on a first predetermined number of bits in a first predetermined set of bit positions of the key register; and

performing an exclusive-or (XOR) operation between (i) a second predetermined number of bits in a second set of predetermined bit positions of the key register and (ii) a value of a round counter for the first plurality of iterations;

store the final state of the key register as a decryption key; and

decrypt the encrypted data block using a second key schedule that includes the plurality of round keys that are generated using the decryption key during a second plurality of iterations.

9. The storage device of claim 8 , wherein decrypting the encrypted data block further comprises:

storing the decryption key into the key register;

initiating the second plurality of iterations starting at a last iteration value and decreasing to a first iteration value; and

during each iteration of the second plurality of iterations:

updating the key register based, at least in part, on a current iteration value; and

generating a round key from the key register using a first number of most significant bits of the key register.

10. The storage device of claim 9 , wherein decrypting the encrypted data block further comprises:

storing the encrypted data block in a data register; and

during each iteration of the second plurality of iterations:

apply the generated round key to the data register by performing an exclusive-or (XOR) operation on the data register using the generated round key.

11. The storage device of claim 9 , wherein updating the key register based, at least in part, on the current iteration value further comprises:

performing an exclusive-or (XOR) operation between (i) a first predetermined number of bits in a first set of predetermined bit positions of the key register and (ii) a value of a round counter for the second plurality of iterations;

performing an inverse non-linear substitution operation on a second predetermined number of bits in a second set of predetermined bit positions of the key register; and

cyclically rotating bits of the key register a predetermined number of bit positions in a predetermined direction.

12. The storage device of claim 8 , wherein cyclically rotating bits of the key register a predetermined number of positions comprises cyclically rotating the bits of the key register the predetermined number of bit positions in a predetermined direction.

13. The storage device of claim 8 , wherein the controller is further configured to:

during each iteration of the first plurality of iterations:

perform an encrypting operation using a round counter previously generated from the key register; and

in parallel with the performing of the encryption, generate a next round counter using the key register to be used during the next iteration.

14. The storage device of claim 8 , wherein the controller is further configured to, during the encrypting:

store the encryption key into the key register;

generate a first round key;

initiate the first plurality of iterations starting at a first iteration value and increasing to a last iteration value; and

during each iteration of the first plurality of iterations:

perform an encrypting operation using a round counter previously generated; and

in parallel with the performing of the encryption, generate a next round counter using the key register to be used during the next iteration.

15. A storage device, comprising:

a non-volatile storage device comprising a plurality of memory dies, the non-volatile storage device including a plurality of memory cells; and

means for encrypting a data block using a first key schedule that includes a plurality of round keys generated from an encryption key, the encrypting resulting in an encrypted data block;

means for modifying a key register during a first plurality of iterations, the key register being updated to a final state after a final iteration of the plurality of iterations, the means for modifying the key register comprising:

means for cyclically rotating bits of the key register a predetermined number of positions;

means for performing a non-linear substitution operation on a first predetermined number of bits in first predetermined bit positions of the key register; and

means for performing an exclusive-or (XOR) operation between (i) a second predetermined number of bits in second predetermined bit positions of the key register and (ii) a value of a round counter for the first plurality of iterations;

means for storing the final state of the key register as a decryption key; and

means for decrypting the encrypted data block using a second key schedule that includes the plurality of round keys that are generated using the decryption key during a second plurality of iterations.

16. The storage device of claim 15 , wherein decrypting the encrypted data block further comprises:

means for storing the decryption key into the key register;

means for initiating the second plurality of iterations starting at a last iteration value and decreasing to a first iteration value; and

during each iteration of the second plurality of iterations:

means for updating the key register based, at least in part, on a current iteration value; and

means for generating a round key from the key register using a first number of most significant bits of the key register.

17. The storage device of claim 16 , wherein decrypting the encrypted data block further comprises:

means for storing the encrypted data block in a data register; and

during each iteration of the second plurality of iterations:

means for applying the generated round key to the data register by performing an exclusive-or (XOR) operation on the data register using the generated round key.

18. The storage device of claim 16 , wherein updating the key register based, at least in part, on the current iteration value further comprises:

means for performing an exclusive-or (XOR) operation between (i) a first predetermined number of bits in predetermined bit positions of the key register and (ii) a value of a round counter for the second plurality of iterations;

means for performing an inverse non-linear substitution operation on a second predetermined number bits in a second set of predetermined bit positions of the key register; and

means for cyclically rotating bits of the key register a predetermined number of bit positions in a predetermined direction.

19. The storage device of claim 15 , further comprising:

during each iteration of the first plurality of iterations:

means for performing an encrypting operation using a round counter previously generated from the key register; and

in parallel with the performing of the encryption, means for generating a next round counter using the key register to be used during the next iteration.

20. The storage device of claim 15 , further comprising, during the encrypting:

means for storing the encryption key into the key register;

means for generating a first round key;

means for initiating the first plurality of iterations starting at a first iteration value and increasing to a last iteration value; and

during each iteration of the first plurality of iterations:

means for performing an encrypting operation using a round counter previously generated; and

in parallel with the performing of the encryption, means for generating a next round counter using the key register to be used during the next iteration.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2022
From: DUMCHIN, YAN; ALON, TZVI; YOSKOVITS, YUVAL
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059771/0341 →