IP Library Granted Patent US 7,594,067
Granted Patent B2
US 7,594,067 · App. 11/582,462 · Granted Sep 22, 2009

Enhanced data access in a storage device

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Quick Facts
Patent No.
US 7,594,067
App. No.
11/582,462
Granted
Sep 22, 2009
Kind
B2
Abstract

A flash storage device having improved write performance is provided. The device includes a storage block having a plurality of physical pages and a controller for mapping the plurality of physical pages to a plurality of logical addresses and for writing data to the plurality of physical pages. When updating data previously written to one of the plurality of logical addresses, the controller is configured to write the updated data to a second physical page which is mapped to the logical address. Each of the logical addresses may be associated with a pointer field, which is for storing a pointer value indicating the invalidity of a physical page and/or the location of another physical page.

Claims (36)

1. A flash storage device comprising:

a storage block having a plurality of physical pages; and

a controller for mapping the plurality of physical pages to a plurality of logical addresses and for writing data to the plurality of physical pages,

wherein, when updating data previously written to one of the plurality of logical addresses, the controller is configured:

to invalidate a first physical page mapped to the logical address, and

to write updated data to a second physical page which is mapped to the logical address wherein the second physical page is located in the storage block in which the first physical page is located.

2. The flash storage device according to claim 1 , wherein the number of physical pages is greater than the number of logical addresses.

3. The flash storage device according to claim 1 , wherein more than one of the plurality of physical pages are allocated to each of the plurality of logical addresses.

4. The flash storage device according to claim 1 , wherein the controller maps the second physical page to the logical address upon flash initialization.

5. The flash storage device according to claim 1 , wherein the controller maps the second physical page to the logical address after receiving a data update for the logical address.

6. The flash storage device according to claim 1 , wherein to invalidate the first physical page mapped to the logical address, the controller is configured to store a pointer value in a pointer field associated with the first physical page, the pointer value indicating the invalidity of the first physical page and the location of the second physical page.

7. The flash storage device according to claim 1 , wherein to invalidate the first physical page mapped to the logical address, the controller is configured to store a pointer value in a pointer field associated with the logical address, the pointer value indicating the invalidity of the first physical page and the location of the second physical page.

8. The flash storage device according to claim 1 , wherein the controller is configured to perform a block carry-over when no other physical pages in the storage block are available to store updated data for the logical address.

9. A flash storage device comprising:

a storage block having a plurality of physical pages; and

a controller for mapping the plurality of physical pages to a plurality of logical addresses and for writing data to the plurality of physical pages,

wherein each of the plurality of logical addresses is associated with a pointer field, and

wherein, when updating data previously written to one of the plurality of logical addresses, the controller is configured:

to store a pointer value in the pointer field associated with the logical address, the pointer value indicating the invalidity of the first physical page and a location of a second physical page, and

to write updated data to the second physical page.

10. The flash storage device of claim 9 , wherein the pointer value comprises an offset value.

11. The flash storage device of claim 9 , wherein the second physical page is located in a different storage block than the first physical page.

12. The flash storage device of claim 9 , wherein the second physical page is located in the storage block in which the first physical page is located.

13. The flash storage device of claim 9 , wherein the storage block includes one or more physical pages which are not initially allocated to any logical address.

14. The flash storage device of claim 9 , wherein the controller is configured to determine a location of a physical page based on a pointer value.

15. The flash storage device of claim 9 , wherein the controller is configured to perform a block carry-over when no other physical pages in the storage block are available to store updated data for a logical address.

16. A method for managing memory operations in a flash storage device, the method comprising:

mapping a plurality of physical pages in a storage block to a plurality of logical addresses;

receiving a write command for one of the plurality of logical addresses;

invalidating a first physical page mapped to the logical address; and

writing updated data to a second physical page which is mapped to the logical address wherein the second physical page is located in the storage block in which the first physical page is located.

17. The method of claim 16 , wherein the number of physical pages is greater than the number of logical addresses.

18. The method of claim 16 , wherein the second physical page is mapped to the logical address upon flash initialization.

19. The method of claim 16 , wherein the second physical page is mapped to the logical address prior to writing updated data to the second physical page.

20. The method of claim 16 , wherein invalidating the first physical page includes storing a pointer value in a pointer field associated with the first physical page, the pointer value indicating the location of the second physical page.

21. The method of claim 16 , further comprising performing a block carry-over when no other physical pages in the storage block are available to store updated data for a logical address.

Assignments (13)
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: SANDISK TECHNOLOGIES, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 069168/0273 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 16, 2018
From: HGST TECHNOLOGIES SANTA ANA, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 046174/0446 →
CHANGE OF NAME Recorded Jul 1, 2015
From: STEC, INC.
To: HGST TECHNOLOGIES SANTA ANA, INC.
Reel/Frame 036042/0390 →
MERGER AND CHANGE OF NAME Recorded Jun 12, 2007
From: SIMPLETECH, INC.
To: STEC, INC.
Reel/Frame 019440/0517 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2006
From: TORABI, HOOSHMAND
To: SIMPLETECH, INC.
Reel/Frame 018434/0475 →