IP Library Granted Patent US 9,905,303
Granted Patent B2
US 9,905,303 · App. 15/133,217 · Granted Feb 27, 2018

Front/back control of integrated circuits for flash dual inline memory modules

Inventors: Ruban Kanapathippillai (Pleasanton, CA); Kenneth Alan Okin (Saratoga, CA)
Assignee: Virident Systems, LLC
G11C16/30G11C5/04G11C5/14G11C16/08H01R12/725H05K1/0286H05K1/181H05K2201/10159H05K2201/10212Y02P70/611Y10T29/49002Y10T29/49117Y10T29/49124Y10T29/49128Y10T29/49169
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Quick Facts
Patent No.
US 9,905,303
App. No.
15/133,217
Granted
Feb 27, 2018
Kind
B2
Abstract

In one implementation, flash memory chips are provided with an operating power supply voltage to substantially match a power supply voltage expected at an edge connector of a dual inline memory module. The one or more of the flash memory chips and a memory support application integrated circuit (ASIC) may be mounted together into a multi-chip package for integrated circuits. The one or more flash memory chips and the memory support ASIC may be electrically coupled together by routing one or more conductors between each in the multi-chip package. The multi-chip package may be mounted onto a printed circuit board (PCB) of a flash memory DIMM to reduce the number of packages mounted thereto and reduce the height of the flash memory DIMM. The number of printed circuit board layers may also be reduced, such as by integrating address functions into the memory support ASIC.

Claims (37)

1. A flash memory dual inline memory module (DIMM) comprising:

a printed circuit board with an edge connector, the printed circuit board having a front side and a back side;

a first plurality of multi-chip packaged flash memory/support application specific integrated circuit (ASIC) parts mounted to the front side of the printed circuit board and electrically coupled to the edge connector, each of the first plurality of multi-chip packaged flash memory/support ASIC parts having

a front side flash memory,

a memory support ASIC, and

a front/back control signal coupled to a first power supply to select a front side pinout of the memory support ASIC;

a second plurality of multi-chip packaged flash memory/support application specific integrated circuit (ASIC) parts mounted to the back side of the printed circuit board and electrically coupled to the edge connector, each of the second plurality of multi-chip packaged flash memory/support ASIC parts having

a back side flash memory,

a memory support ASIC, and

a front/back control signal coupled to a second power supply to select a back side pinout of the memory support ASIC that mirrors the front side pinout of the memory support ASIC; and

a first address device mounted to the printed circuit board and electrically coupled to the edge connector and the first plurality of multi-chip packaged flash memory/support ASIC parts.

2. The flash memory DIMM of claim 1 , further comprising:

a plurality of first metal traces on one or more layers of the printed circuit board, the plurality of metal traces to electrically couple the edge connector and the plurality of multi-chip packaged flash memory/support ASIC parts, and

wherein the plurality of metal traces include traces for power, ground, and address and data signals.

3. The flash memory DIMM of claim 1 , wherein

the first power supply is a positive power supply to select the front side pinout of the memory support ASIC in each of the first plurality of multi-chip packaged flash memory/support ASIC parts; and

the second power supply is a negative power supply to select the back side pinout of the memory support ASIC in each of the second plurality of multi-chip packaged flash memory/support ASIC parts.

4. The flash memory DIMM of claim 3 , wherein

the negative power supply is ground.

5. The flash memory DIMM of claim 3 , wherein

the front/back control signal electronically alters the pinout configuration of the memory support ASIC to provide the mirrored pinout.

6. The flash memory DIMM of claim 5 , wherein

the mirrored pinout reduces conductive traces on the printed circuit board and the number of layers of conductive traces.

7. A dual inline memory module (DIMM) comprising:

a printed circuit board with an edge connector, the printed circuit board having a front side and a back side;

a first plurality of integrated circuit parts mounted to the front side of the printed circuit board and electrically coupled to the edge connector, each of the first plurality of integrated circuit parts having a front/back control signal coupled to a first power supply to select a front side pinout of an integrated circuit die within each integrated circuit part; and

a second plurality of integrated circuit parts mounted to the back side of the printed circuit board and electrically coupled to the edge connector, each of the second plurality of integrated circuit parts having a front/back control signal coupled to a second power supply to select a back side pinout of an integrated circuit die within each integrated circuit part;

wherein the selected back side pinout of the integrated circuit die within each of the second plurality of integrated circuit parts mirrors the selected front side pinout of the integrated circuit die within each of the first plurality of integrated circuit parts.

8. The DIMM of claim 7 , wherein

the first power supply is a positive power supply to select the front side pinout of the integrated circuit die in each of the first plurality of integrated circuit parts; and

the second power supply is a negative power supply to select the back side pinout of the integrated circuit die in each of the second plurality of integrated circuit parts.

9. The DIMM of claim 8 , wherein

the negative power supply is ground.

10. The DIMM of claim 7 , wherein

the front/back control signal electronically alters the pinout configuration of the integrated circuits to provide the mirrored pinout.

11. The DIMM of claim 10 , wherein

the mirrored pinout reduces conductive traces on the printed circuit board and the number of layers of conductive traces.

Assignments (12)
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: SANDISK TECHNOLOGIES, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 069168/0273 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 053926 FRAME 0446 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0321 →
SECURITY INTEREST Recorded Sep 29, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053926/0446 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2020
From: VIRIDENT SYSTEMS, LLC
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 053180/0472 →
CHANGE OF NAME Recorded May 10, 2017
From: VIRIDENT SYSTEMS, INC.
To: VIRIDENT SYSTEMS, LLC
Reel/Frame 042438/0240 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 21, 2016
From: KANAPATHIPPILLAI, RUBAN; OKIN, KENNETH A
To: VIRIDENT SYSTEMS, INC.
Reel/Frame 038337/0120 →
Continuity (6)
Continuation 14016235 · Sep 3, 2013
Division 13457170 · Apr 26, 2012
Division 11876479 · Oct 22, 2007
Provisional Application 60892864 · Mar 4, 2007
Provisional Application 60862597 · Oct 23, 2006
Related Publication 20160254061A1 · Sep 1, 2016