Word-line inter-cell interference detector in flash system
View Patent ↗Aspects of the subject technology encompass a method for retrieving information stored in flash memory. In certain implementations, the method can include operations for reading a plurality of memory cells in a word line, generating a plurality of read signals based on the reading of the plurality of memory cells and identifying, from among the plurality of read signals, a first read signal associated with a first memory cell and a second read signal associated with a second memory cell, wherein the first memory cell is adjacent to the second memory cell in the word line. In certain aspects, the method can further include operations for generating an output for the first memory cell, wherein the output is based on the first and second read signals. A data storage system and article of manufacture are also provided.
1. A method for retrieving information stored in flash memory, comprising:
obtaining a plurality of read signals from a plurality of memory cells;
identifying, from among the plurality of read signals, a first read signal associated with a first memory cell and a second read signal associated with a second memory cell, wherein the first memory cell is adjacent to the second memory cell in a word line; and
generating an output for the first memory cell, wherein the output is based on the first and the second read signals.
2. The method of claim 1 , further comprising:
decoding the first read signal based on the output.
3. The method of claim 1 , further comprising:
identifying, from among the plurality of read signals, a third read signal associated with a third memory cell adjacent to the first memory cell, and
wherein the output is further based on the third read signal associated with the third memory cell.
4. The method of claim 1 , wherein generating the output further comprises:
determining a programming level associated with the second memory cell based on the second read signal; and
selecting the output based on the programming level associated with the second memory cell.
5. The method of claim 1 , wherein generating the output further comprises:
referencing a trellis having a plurality of transition states, wherein each of the transition states comprises an initial state and an end state, and
wherein each of the initial state and the end state comprises data levels of two adjacent cells.
6. The method of claim 1 , wherein the output comprises one or more of a log-likelihood ratio (LLR) and an a posteriori probability (APP).
7. The method of claim 1 , wherein the output is based on one or more of retention characteristics and endurance characteristics associated with the flash memory.
8. The method of claim 1 , wherein the first read signal and the second read signal comprise hard decision information.
9. The method of claim 1 , wherein the first read signal and the second read signal comprise soft decision information.
10. The method of claim 1 , wherein the output is based on inter-cell interference data corresponding with one or more programming levels.
11. A data storage system, comprising:
a configuration memory;
a plurality of memory cells; and
a controller coupled to the configuration memory and the plurality of memory cells, wherein the controller is configured to perform operations for:
obtaining a plurality of read signals based on the reading of the plurality of memory cells;
identifying, from among the plurality of read signals, a first read signal associated with a first memory cell and a second read signal associated with a second memory cell, wherein the first memory cell is adjacent to the second memory cell in a word line; and
generating an output for the first memory cell, wherein the output is based on the first and the second read signals.
12. The data storage system of claim 11 , wherein the controller is further configured to perform steps for:
decoding the first read signal based on the output.
13. The data storage system of claim 11 , wherein the controller is further configured to perform steps for:
identifying, from among the plurality of read signals, a third read signal associated with a third memory cell adjacent to the first memory cell, and
wherein the output is further based on the third read signal associated with the third memory cell.
14. The data storage system of claim 11 , wherein generating the output further comprises:
determining a programming level associated with the second memory cell based on the second read signal; and
selecting the output based on the programming level associated with the second memory cell.
15. The data storage system of claim 11 , wherein generating the output further comprises:
referencing a trellis having a plurality of transition states, wherein each of the transition states comprises an initial state and an end state, and
wherein each of the initial state and the end state comprises data levels of two adjacent cells.
16. The data storage system of claim 11 , wherein the output comprises one or more of a log-likelihood ratio (LLR) and an a posteriori probability (APP).
17. The data storage system of claim 11 , wherein the output is based on one or more of retention characteristics and endurance characteristics.
18. The data storage system of claim 11 , wherein the first read signal and the second read signal comprise hard decision information.
19. The data storage system of claim 11 , wherein the first read signal and the second read signal comprise soft decision information.
20. The data storage system of claim 11 , wherein the output is based on inter-cell interference data corresponding with one or more programming levels.
21. An article of manufacture for mitigating effects of inter-cell interference in an electronic storage, the article of manufacture comprising:
at least one non-transitory processor readable storage medium; and
instructions stored on the at least one medium, wherein the instructions are configured to be readable from the at least one medium by at least one processor and thereby cause the at least one processor to perform operations for:
obtaining a plurality of read signals based on the reading of the plurality of memory cells;
identifying, from among the plurality of read signals, a first read signal associated with a first memory cell and a second read signal associated with a second memory cell, wherein the first memory cell is adjacent to the second memory cell in a word line; and
generating an output for the first memory cell, wherein the output is based on the first and second read signals.
22. The article of manufacture of claim 21 , wherein the processor is configured to perform operations for:
decoding the first read signal based on the output.
23. The article of manufacture of claim 21 , wherein the processor is configured to perform operations for:
identifying, from among the plurality of read signals, a third read signal associated with a third memory cell adjacent to the first memory cell, and
wherein the output is further based on the third read signal associated with the third memory cell.