Elastic buffer based asymmetric pipeline FIFO process
The present disclosure generally relates to efficient management of an elastic buffer. Efficient management can be achieved by using an asymmetric asynchronous First In, First Out (FIFO) approach based on normalization of write and read pointers. The normalization is done in accordance with the FIFO depth while keeping a single bit change approach. In order to achieve an asymmetric dynamic ability for part per million (PPM) compensation, a plurality of sub-FIFOs are used for opponent side pointer synchronization. Combining the features allows for creating an asynchronous asymmetric FIFO with pipeline characteristics.
1. A data storage device, comprising:
one or more memory devices; and
a controller coupled to the one or more memory devices, wherein:
the controller is configured to deliver data to a host device according to an asynchronous asymmetric First In, First Out (FIFO) process;
the asynchronous asymmetric FIFO process comprises calculating a minimum index value and a maximum index value; and
the minimum index value is a lower bound of a memory depth range and the maximum index value is an upper bound of the memory depth range.
2. A data storage device, comprising:
one or more memory devices; and
a controller coupled to the one or more memory devices, wherein the controller is configured to deliver data to a host device according to an asynchronous asymmetric First In, First Out (FIFO) process, wherein:
the asynchronous asymmetric FIFO process comprises calculating a minimum index value and a maximum index value; and
the minimum index value is calculated according to the following formula:
((required depth rounded to the power of 2)/2)−((required depth)/2)
wherein the required depth is a number of index entries times two to account for full and empty status, and where rounded to the power of 2 is an even number of a geometric sequence starting at 2 with a common ratio of 2.
3. The data storage device of claim 2 , wherein the maximum index value is calculated according to the following formula:
((required depth rounded to the power of 2)/2)+((required depth)/2)−1.
4. A data storage device, comprising:
one or more memory devices; and
a controller coupled to the one or more memory devices, wherein the controller comprises:
a main First In, First Out (FIFO) chip;
a write FIFO chip coupled to the main FIFO chip;
a read FIFO chip coupled to the main FIFO chip;
a write sub-FIFO chip array, wherein the write sub-FIFO chip array is coupled to the write FIFO chip and the read FIFO chip; and
a read sub-FIFO chip array, wherein the read sub-FIFO chip array is coupled to the write FIFO chip and the read FIFO chip; wherein:
the write FIFO chip is capable of sending signals to the main FIFO chip and the read sub-FIFO chip array concurrently;
the read FIFO chip is capable of sending signals to the main FIFO chip and the write sub-FIFO chip array concurrently;
the read FIFO chip is configured to send a read address to the main FIFO chip;
the read FIFO chip is configured to send a read pointer to the write sub-FIFO chip array; and
the write sub-FIFO chip array is configured to deliver a write double clock read pointer to the write FIFO chip.
5. The data storage device of claim 4 , wherein the write sub-FIFO chip array contains a first plurality of sub-FIFO chips, wherein the read sub-FIFO chip array contains a second plurality of sub-FIFO chips, and wherein the first plurality is equal to the second plurality.
6. The data storage device of claim 4 , wherein the write FIFO chip is configured to send a write address to the main FIFO chip, wherein the write FIFO chip is configured to send a write pointer to the read sub-FIFO chip array.
7. The data storage device of claim 6 , wherein the read sub-FIFO chip array is configured to deliver a read double clock write pointer to the read FIFO chip.
8. The data storage device of claim 4 , wherein the write sub-FIFO chip array is configured to receive a write clock signal and a negative write to read signal.
9. The data storage device of claim 8 , wherein the read sub-FIFO chip array is configured to receive a read clock signal and a negative read to write signal.
10. The data storage device of claim 9 , wherein the write FIFO chip is configured to receive the write clock signal and wherein the read FIFO chip is configured to receive the read clock signal.
11. The data storage device of claim 10 , wherein the write FIFO chip is configured to receive the negative write to read signal and wherein the read FIFO chip is configured to receive the negative read to write signal.
12. The data storage device of claim 4 , wherein the main FIFO chip is configured to receive a write clock enable signal.
13. The data storage device of claim 12 , wherein the main FIFO chip is configured to receive a write data signal and wherein the main FIFO chip is configured to send a read data signal.
14. The data storage device of claim 4 , wherein the main FIFO chip is a dual port random access memory (RAM).