Granted Patent B2

US 10,642,536 · App. 15/912,944 · Granted May 5, 2020

Abstract

Claims (88)

1. A memory system, comprising:

non-volatile memory; and

a controller connected to the non-volatile memory, wherein the controller is configured to:

write a set of commands to an alternate data structure in a physical memory of a host,

switch a command pointer from referencing a primary data structure to referencing the alternate data structure, and

in response to the command pointer being switched, execute against the alternate data structure rather than the primary data structure.

2. The memory system of claim 1 , wherein:

the primary data structure is created by the host;

the alternate data structure is created in response to a request from the controller; and

the controller is further configured to:

receive the set of commands from the primary data structure in the physical memory of the host,

execute the commands, and

after executing the commands, replay the set of commands by the writing of the set of commands to the alternate data structure and executing against the alternate data structure.

3. The memory system of claim 1 , wherein:

the controller is configured to execute against the alternate data structure by transmitting the set of commands from the host to the memory system and executing the commands from the memory system; and

the host is external to and configured to be connected to the memory system.

4. The memory system of claim 1 , wherein the controller is further configured to:

receive the set of commands from the host;

store the set of commands in a log in the memory system prior to writing the set of commands to the alternate data structure; and

write the set of commands to the alternate data structure from the log.

5. The memory system of claim 4 , wherein the controller is further configured to:

store, in the log, timing information for the set of commands; and

use the timing information to execute the set of commands from the alternate data structure.

6. The memory system of claim 1 , wherein the controller is further configured to:

execute the set of commands; and

after executing the set of commands, replay the set of commands by the executing against the alternate data structure.

7. The memory system of claim 6 , wherein the controller is further configured to:

when replaying the set of commands:

assert a pause flag to the host prior to executing against the alternate data structure; and

remove the pause flag subsequent to executing against the alternate data structure.

8. The memory system of claim 6 , wherein the controller is further configured to:

when replaying the set of commands:

complete current active commands;

assert a pause flag to the host prior to executing against the alternate data structure;

allocate memory space in the host's physical memory for the alternate data structure;

trigger execution of the set of commands in the alternate data structure; and

remove the pause flag to the host subsequent to executing against the alternate data structure.

9. The memory system of claim 1 , wherein:

the primary data structure is a first queue created and managed by the host and on the host; and

the alternate data structure is a second queue on the host.

10. The memory system of claim 1 , wherein:

the alternate data structure includes an alternate submission queue and an alternate completion queue; and

the primary data structure includes a primary submission queue and a primary completion queue in the host's physical memory.

11. The memory system of claim 10 , wherein:

the command pointer comprises a submission queue tail pointer; and

the controller is further configured to:

maintain a submission queue head pointer, a completion queue head pointer, and a completion queue tail pointer;

switch the submission queue head pointer, the completion queue head pointer, and the completion queue tail pointer from referencing the primary data structure to referencing the alternate data structure; and

execute against the alternate data structure by:

using the submission queue tail pointer and the submission queue head pointer to access one or more commands in the alternate submission queue and execute the one or more commands;

using the completion queue head pointer and the completion queue tail pointer to insert one or more completion entries in the alternate completion queue; and

after inserting one or more completion entries in the alternate completion queue, interrupting the host.

12. The memory system of claim 1 , wherein:

the non-volatile memory and the controller are part of a solid state drive; and

the controller is further configured to implement a NVM Express interface with the host.

13. A method comprising:

a solid state drive saving a set of commands in a memory on a host system connected to the solid state drive;

transmitting the commands from the memory on the host system to the solid state drive;

executing the transmitted commands on the solid state drive; and

the solid state drive executing the set of commands prior to the saving the set of commands in the memory on the host system;

wherein the saving the set of commands in the memory on the host system, the transmitting the commands, and the executing the transmitted commands together comprise the solid state drive re-executing the set of commands.

14. The method of claim 13 , further comprising:

the solid state drive storing the set of commands in a log when executing the set of commands prior to the saving the set of commands in the memory on the host system,

wherein the saving the set of commands in the memory on the host system comprises:

reading the set of commands from the log; and

transmitting the set of commands read to the memory on the host system.

15. The method of claim 13 , further comprising:

the solid state drive indicating to the host to pause sending commands for memory operations when re-executing the set of commands.

16. An apparatus, comprising:

a host interface configured to be connected to a host;

a memory interface configured to be connected to non-volatile memory; and

a processor connected to the host interface and the memory interface, wherein the processor is configured to:

execute a sequence of commands for memory operations, and

replay the sequence of commands by writing a copy of the sequence of commands to physical memory on the host via the host interface and executing the copy of the sequence of commands from the physical memory on the host.

17. The apparatus of claim 16 , further comprising a local memory connected to the processor and configured to:

store the copy of the sequence of commands to be written to the physical memory on the host; and

store a pointer to a first memory structure on the host,

wherein:

the processor is further configured to change the pointer to reference a second memory structure on the host in response to the processor replaying the sequence of commands; and

the copy of the sequence of commands is stored in the second memory structure on the host.

18. A solid state drive, comprising:

a non-volatile memory die; and

a controller connected to the non-volatile memory die and configured to communicate with a host external to the solid state drive, the controller comprising:

a command log configured to store a sequence of commands received from a host, and

means for replaying the sequence of commands after the sequence of commands has been executed by the controller by reading the commands from the command log, writing the commands read to a memory on the host, and executing, at the controller, the commands from the memory on the host.

19. The solid state drive of claim 18 , wherein the controller is further configured to:

execute the sequence of commands prior to replaying the sequence of commands; and

store the sequence of commands in the command log in coordination with the executing the sequence of commands prior to replaying.

Assignments (10)