Data storage device and method for power on reset and read error handling
A data storage device has a controller that instructs a memory to read memory cells using a number of different read voltage levels and then selects the read voltage level that provides the best read. Instead of sending individual commands for each of the different read voltage levels, the controller sends a single command that specifies an initial read voltage level and a voltage shift, and the memory automatically increments the read voltage level by the voltage shift for each read.
1. A data storage device comprising:
a memory comprising a plurality of memory cells; and
a controller coupled with the memory and configured to:
send a first command to the memory that specifies an initial read voltage threshold and a voltage shift;
send a second command to the memory a plurality of times, wherein the memory is configured to, each time in response to receiving the second command:
(a) read data from the plurality of memory cells using a read voltage threshold;
(b) send the data read from the plurality of memory cells to the controller; and
(c) increment the read voltage threshold by a multiple of the voltage shift;
wherein:
a first time the memory receives the second command, the plurality of memory cells are read using the initial read voltage threshold;
each subsequent time the memory receives the second command, the plurality of memory cells are read using the initial read voltage threshold incremented by a different multiple of the voltage shift; and
the memory incrementing the read voltage threshold in response to receiving the second commands avoids a latency that would be incurred by the controller specifying an incremented read voltage threshold.
2. The data storage device of claim 1 , wherein the controller is further configured to:
set a variable that specifies the plurality of times; and
perform a loop to send the second command to the memory, wherein the loop is repeated based on the variable.
3. The data storage device of claim 1 , wherein the second command comprises a setFeature command.
4. The data storage device of claim 1 , wherein the plurality of times is configured is by the controller.
5. The data storage device of claim 1 , wherein the controller is further configured to:
perform error correction and determine a number of errors contained in data received from the memory; and
select a read voltage threshold associated with the data received from the memory that contains a fewest number of errors.
6. The data storage device of claim 1 , wherein the first command comprises a subcommand that specifies the initial read voltage threshold.
7. The data storage device of claim 6 , wherein the second command further comprises a subcommand for automatically incrementing the multiple of the voltage shift.
8. The data storage device of claim 1 , wherein the plurality of memory cells comprise single-level cells.
9. The data storage device of claim 1 , wherein the plurality of memory cells comprise multi-level cells.
10. The data storage device of claim 1 , wherein the memory comprises a three-dimensional memory.
11. The data storage device of claim 1 , wherein the second command comprises a die select field, a setFeature prefix, a selection of a state to be read, a delta level to use for each state, a dynamic read command, an identification of memory to read, a sense command, and/or a toggle data sequence.
12. In a memory of a data storage device, a method comprising:
receiving, from a controller of the data storage device, a first command specifying an initial voltage level and a digital-to-analog converter (DAC) shift;
receiving, from the controller of the data storage device, a second command a plurality of times; and
each time in response to receiving the second command:
(a) reading data from a plurality of memory cells in the memory using a read voltage level;
(b)
sending the data read from the plurality of memory cells to the controller; and
(c) incrementing the read voltage threshold by a multiple of the DAC shift;
wherein:
a first time the memory receives the second command, the plurality of memory cells are read using the initial read voltage threshold;
each subsequent time the memory receives the second command, the plurality of memory cells are read using the initial read voltage threshold incremented by a different multiple of the DAC shift; and
the memory incrementing the read voltage threshold in response to receiving the second commands avoids a latency that would be incurred by the controller specifying an incremented read voltage threshold.
13. The method of claim 12 , wherein the memory performs (a)-(c) in response to receiving the initial voltage level from the controller only a single time.
14. The method of claim 12 , wherein the plurality of times is configured by the controller.
15. The method of claim 12 , wherein the first command comprises a subcommand that specifies the initial voltage level and the DAC shift.
16. The method of claim 12 , further comprising performing a bit-error-rate estimate and scan (BES) operation, wherein (a)-(c) are performed as part of the BES operation.
17. The method of claim 12 , further comprising performing an initialization process, wherein (a)-(c) are performed as part of the initialization process.
18. The method of claim 12 , further comprising performing a read error handling (REH) process, wherein (a)-(c) are performed as part of the REH process.
19. The method of claim 12 , further comprising performing a cell voltage distribution (CVD) process, wherein (a)-(c) are performed as part of the CVD process.
20. A memory in a data storage device, the memory comprising:
a plurality of memory cells;
means for receiving, from a controller of the data storage device, a first command specifying an initial voltage level and a digital-to-analog converter (DAC) shift;
means for receiving, from the controller of the data storage device, a second command a plurality of times; and
means for each time in response to receiving the second command:
(a) reading data from a plurality of memory cells in the memory using a read voltage level;
(b) sending the data read from the plurality of memory cells to the controller; and
(c) incrementing the read voltage threshold by a multiple of the DAC shift;
wherein:
a first time the memory receives the second command, the plurality of memory cells are read using the initial read voltage threshold;
each subsequent time the memory receives the second command, the plurality of memory cells are read using the initial read voltage threshold incremented by a different multiple of the DAC shift; and
the memory incrementing the read voltage threshold in response to receiving the second commands avoids a latency that would be incurred by the controller specifying an incremented read voltage threshold.