IP Library Granted Patent US 11,765,911
Granted Patent B2
US 11,765,911 · App. 17/590,561 · Granted Sep 19, 2023

Method of making magnetoresistive memory cell over a selector pillar

Inventors: Lei Wan (San Jose, CA); Jordan Katine (Mountain View, CA); Neil Robertson (Palo Alto, CA)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
H10B61/10G11C11/161G11C11/1659H10B61/22H10N50/01H10N50/80G11C11/1655G11C11/1657G11C11/1673H10N50/10
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Quick Facts
Patent No.
US 11,765,911
App. No.
17/590,561
Granted
Sep 19, 2023
Kind
B2
Abstract

A spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) device includes a SOT MRAM cell containing a first two terminal selector element, a nonmagnetic metallic assist plate, and a magnetic tunnel junction located between the first two terminal selector element and the nonmagnetic metallic assist plate, and a circuit selection element selected from a transistor or a second two terminal selector element electrically connected to the nonmagnetic metallic assist plate of the SOT MRAM cell.

Claims (31)

1. A method of forming a magnetoresistive memory device, comprising:

forming first electrically conductive lines over a substrate;

forming a two-dimensional array of pillars each comprising a selector element over the first electrically conductive lines;

forming a layer stack over the two-dimensional array of pillars, the layer stack comprising an unpatterned magnetic free layer, an unpatterned magnetic reference layer and an unpatterned tunneling dielectric layer located between the unpatterned magnetic free layer and the unpatterned magnetic reference layer; and

patterning the layer stack to form a two-dimensional array of vertical stacks over the two-dimensional array of pillars, wherein each of the vertical stacks comprises a magnetic free layer, a magnetic reference layer and a tunneling dielectric layer located between magnetic free layer and the magnetic reference layer; and

forming second electrically conductive lines over the two-dimensional array of vertical stacks;

wherein the selector element comprises an ovonic threshold switch material portion.

2. The method of claim 1 , wherein the ovonic threshold switch material portion comprises a chalcogenide material.

3. The method of claim 1 , wherein the pillars comprise rectangular pillars.

4. The method of claim 3 , wherein each of the rectangular pillars includes a stack of the ovonic threshold switch material portion and a metal pillar structure.

5. The method of claim 3 , further comprising forming an insulating liner in line trenches located between the rectangular pillars prior to forming the layer stack.

6. The method of claim 5 , wherein the layer stack is formed over the two-dimensional array of rectangular pillars and over the insulating liner.

7. The method of claim 1 , wherein:

the layer stack further comprises a synthetic antiferromagnetic material layer stack; and

the unpatterned magnetic reference layer comprises a portion of the synthetic antiferromagnetic material layer stack.

8. The method of claim 7 , wherein:

each of the vertical stacks further comprises a synthetic antiferromagnetic structure; and

each magnetic reference layer comprises a portion of the synthetic antiferromagnetic structure.

9. The method of claim 1 , wherein the magnetic free layer comprises CoFe or CoFeB.

10. The method of claim 9 , wherein the magnetic reference layer comprises CoFe or CoFeB.

11. The method of claim 10 , wherein the tunneling dielectric layer comprises MgO.

12. The method of claim 10 , wherein the magnetic free layer, the magnetic reference layer and the tunneling dielectric layer form a magnetic tunnel junction.

13. The method of claim 1 , wherein the step of patterning the layer stack comprises:

forming a patterned photoresist layer over the layer stack; and

etching the layer stack using the patterned photoresist layer as a mask.

14. The method of claim 1 , wherein each of the vertical stacks comprises a magnetoresistive random access memory (MRAM) cell.

15. The method of claim 14 , wherein the two-dimensional array of vertical stacks comprises a two-dimensional array of MRAM cells.

16. The method of claim 15 , wherein the two-dimensional array of MRAM cells has a same two-dimensional periodicity as the two-dimensional array of pillars.

17. The method of claim 16 , wherein the two-dimensional array of pillars comprises a two-dimensional array of rectangular pillars.

18. The method of claim 17 , wherein the MRAM cells are not rectangular.

19. The method of claim 17 , wherein at least one sidewall of the MRAM cells is laterally offset from a corresponding sidewall of the underlying rectangular pillar.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2022
From: WAN, LEI; KATINE, JORDAN; ROBERTSON, NEIL
To: WESTERN DIGITAL TECHNOLOGIES, INC.,
Reel/Frame 058850/0434 →
Continuity (2)
Continuation 16401172 · May 2, 2019
Related Publication 20220157885A1 · May 19, 2022