IP Library Granted Patent US 11,289,395
Granted Patent B2
US 11,289,395 · App. 16/821,860 · Granted Mar 29, 2022

Aperture structure on semiconductor component backside to alleviate delamination in stacked packaging

Inventors: Junrong Yan (Minhang District, CN); Chee Keong Chin (Shanghai, CN); Xin Lu (Shanghai, CN)
Assignee: Western Digital Technologies, Inc.
H01L23/3142H01L21/50H01L21/67011H01L23/31H01L25/0657
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Quick Facts
Patent No.
US 11,289,395
App. No.
16/821,860
Granted
Mar 29, 2022
Kind
B2
Abstract

A process includes forming one or more apertures on a component backside, creating a vacuum in a mold chase, and engaging the component backside with a mold compound in the mold chase. The one or more apertures form an aperture structure. The aperture structure may include multiple apertures parallel or orthogonal to each other. The apertures have an aperture width, aperture depth, and aperture pitch. These characteristics may be altered to minimize the likelihood of trapped air remaining after creating the vacuum in the mold chase.

Claims (14)

1. A semiconductor package, comprising:

a first semiconductor component having a backside portion positioned on a second semiconductor component; and

wherein the backside portion of the first semiconductor component includes one or more apertures to allow air to flow between the first semiconductor component and the second semiconductor component, wherein each aperture has an aperture width of between about 10 μm to about 20 μm, and wherein parallel apertures have an aperture pitch of between about 100 μm to about 1 mm.

2. The semiconductor package of claim 1 , wherein the one or more apertures comprises a first set of multiple parallel apertures.

3. The semiconductor package of claim 2 , wherein the first set of multiple parallel apertures have an aperture pitch, the aperture pitch being lesser toward a center of the backside portion.

4. The semiconductor package of claim 2 , wherein the one or more apertures further comprises a second set of multiple parallel apertures orthogonal to the first set of multiple parallel apertures forming a matrix of apertures.

5. The semiconductor package of claim 1 , wherein the backside portion comprises a component length longer than a component width, the one or more apertures comprising a first aperture bisecting the backside portion and extending from edge to edge across the component length.

6. A semiconductor package, comprising:

a first semiconductor component having a backside portion positioned on a second semiconductor component;

wherein the backside portion of the first semiconductor component includes one or more apertures to allow air to flow between the first semiconductor component and the second semiconductor component;

wherein the backside portion comprises a component length longer than a component width, the one or more apertures comprising a first aperture bisecting the backside portion and extending from edge to edge across the component length; and

wherein the one or more apertures further comprises a second aperture bisecting the backside portion and extending from edge to edge of the component width.

7. The semiconductor package of claim 6 , wherein the first aperture and the second aperture are orthogonal apertures.

8. The semiconductor package of claim 6 , wherein the first aperture and the second aperture are not orthogonal.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 053482 FRAME 0453 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0279 →
SECURITY INTEREST Recorded May 14, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053482/0453 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 23, 2020
From: LU, XIN; CHIN, CHEE KEONG; YAN, JUNRONG
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 052473/0511 →