Network computer systems with power management
View Patent ↗In one embodiment of the invention, a memory apparatus is disclosed. The memory apparatus includes a memory array, a block read/write controller, and a random access read memory controller. The memory array is block read/write accessible and random read accessible. The block read/write controller is coupled between the memory array and an external interconnect. The block read/write controller performs block read/write operations upon the memory array to access blocks of consecutive memory locations therein. The random access read memory controller is coupled between the memory array and the external interconnect in parallel with the block read/write access controller. The random access read memory controller performs random read memory operations upon the memory array to access random memory locations therein.
1. An apparatus comprising:
a network computer system including:
a plurality of processor complexes, where each processor complex has a plurality of processor cores;
a plurality of disk-read-only-memory (disk-ROM) devices shared amongst the plurality of processor complexes, wherein a disk-ROM is an electronic solid state device including a memory space formed of non-volatile memory circuit cells;
a router coupled to the plurality of processor cores and the plurality of disk-ROM devices;
a plurality of external interconnects coupling the plurality of processor complexes to the plurality of disk-ROM devices, wherein the plurality of external interconnects and the plurality of disk-ROM devices are external to the plurality of processor complexes, wherein a first processor core of the plurality of processor complexes is coupled directly to a first disk-ROM device of the plurality of disk-ROM devices, wherein the first processor core is directly coupled to the router and wherein a second processor core of the plurality of processor complexes is coupled to the first disk-ROM device through the router;
a power controller coupled to each of the plurality of processor complexes, the power controller to power down one or more processor complexes in response to a reduced computing load; and
wherein the plurality of disk-ROM devices remain powered on and maintain data for one or more processor complexes that remain powered on.
2. The apparatus of claim 1 , wherein the power controller executes a centralized network control software driver to make consistent network-level decisions of the one or more processor complexes that remain powered on and one or more processor complexes that are powered down in response to the computing load on the network computer system.
3. The apparatus of claim 1 , wherein the network computer system further includes:
a router coupled to the plurality of processor complexes and the plurality of disk-read-only-memory (disk-ROM) devices; and
an interconnect network coupled between the router, the plurality of processor complexes, and the plurality of disk-read-only-memory (disk-ROM) devices;
wherein the interconnect network to communicate information between the plurality of processor complexes and the plurality of disk-read-only-memory (disk-ROM) devices using one or more packets
wherein the interconnect network includes the plurality of external interconnects.
4. The apparatus of claim 3 , wherein:
each processor complex executes a distributed network control software driver that is in communication with the power controller and the other processor complexes to cooperate and make consistent network-level decisions of the one or more processor complexes that remain powered up and the one or more processor complexes that are powered down in response to the computing load on the network computer system.
5. The apparatus of claim 3 , wherein each processor complex has:
a processor address space that includes pointers pointing to a portion of physical address space associated with at least one of the plurality of disk-read-only-memory (disk-ROM) devices.
6. The apparatus of claim 5 , wherein each processor complex includes:
a plurality of processors with each processor having an application memory space pointing to a portion of the processor address space of the processor complex.
7. The apparatus of claim 6 , wherein each processor complex includes:
a plurality of memory devices to provide a physical memory space and wherein each processor complex has processor address space that includes pointers pointing to a portion of physical memory space associated with one or more of the plurality of memory devices.
8. An apparatus comprising:
a network computer system including:
a plurality of processor complexes, wherein each processor complex has a plurality of processor cores;
a plurality of disk-read-only-memory (disk-ROM) devices shared amongst the plurality of processor complexes, wherein a disk-ROM device is an electronic solid state device including a memory space formed of non-volatile memory circuit cells;
a plurality of external interconnects coupling the plurality of processor complexes to the plurality of disk-ROM devices, wherein the plurality of external interconnects and the plurality of disk-ROM devices are external to the plurality of processor complexes;
a power controller coupled to each of the plurality of processor complexes, the power controller to power down one or more processor complexes in response to a reduced computing load; and
wherein the plurality of disk-ROM devices remain powered on and maintain data for one or more processor complexes that remain powered on, wherein:
each processor complex includes a cache coherency system; and
the plurality of external interconnects are not subject to the cache coherency system of each processor complex.
9. The apparatus of claim 8 , wherein:
each processor complex includes:
one or more levels of cache memory;
a cache-coherent interconnect network coupled to the one or more levels of cache memory; and
a bridge port coupled to and between the external interconnect network and the cache-coherent interconnect network.
10. The apparatus of claim 9 , wherein
data in the plurality of disk-read-only-memory (disk-ROM) devices is maintained in a cache coherent state with each processor complex by a mapping software driver executed by each processor complex.
11. The apparatus of claim 1 , wherein
the plurality of disk-ROM devices have a shared disk-ROM space that is maintained when one or more processor complexes are powered down.
12. An apparatus, comprising:
a network computer system including:
a plurality of processor complexes, wherein each processor complex has a plurality of processor cores;
a first means for storing data; and
a router, wherein a first processor complex of the plurality of processor complexes is coupled directly to the first means for storing data and the router, and wherein a second processor complex of the plurality of processor complexes is coupled to the first means for storing data through the router, and wherein the first means for storing data is distinct from the first processor complex.
13. The apparatus of claim 12 , further comprising a second means for storing data, wherein the second processor complex is coupled directly to the second means for storing data.
14. The apparatus of claim 13 , wherein the first processor complex is coupled to the second means for storing data through the router.
15. The apparatus of claim 13 , wherein the first means for storing data is capable of being written a whole data block at a time.
16. The apparatus of claim 15 , wherein the first means for storing data is capable of being read one byte at a time.