IP Library Granted Patent US 11,978,490
Granted Patent B2
US 11,978,490 · App. 17/752,112 · Granted May 7, 2024

Back pattern counter measure for solid state drives

Inventors: Ming Jin (Fremont, CA); Yongke Sun (Pleasanton, CA); Lanlan Gu (San Jose, CA)
Assignee: Western Digital Technologies, Inc.
G11C11/1657G11C11/1673G11C11/4087
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Quick Facts
Patent No.
US 11,978,490
App. No.
17/752,112
Granted
May 7, 2024
Kind
B2
Abstract

This disclosure includes back pattern counter measures for solid state drives. Embodiments described herein include setting and applying read threshold offsets according to flags set based on an amount of data stored within a memory block (e.g., an “openness” of the block). The flag is implemented during read commands to account for shifts in voltage distribution of open blocks. A value of the flag may be chosen based on a number of word lines included in the block that store data. The read threshold offsets may further be based on at least one of the set flag or an age of a respective NAND cell.

Claims (58)

1. A data storage device, comprising:

a memory interface configured to interface with a non-volatile memory; and

an electronic processor configured to:

receive a read command to read data stored in a block of the non-volatile memory,

determine a last coded word line of the block,

set a flag indicative of the last coded word line that is determined,

determine a read threshold offset value based on the last coded word line of the block, and

perform a read command using the read threshold offset value that is determined.

2. The data storage device of claim 1 , wherein the electronic processor is further configured to:

set the flag indicative of the last coded word line within a flash module descriptor.

3. The data storage device of claim 1 , wherein the electronic processor is further configured to:

determine whether the block is an open block, and

perform, in response to determining that the block not the open block, the read command.

4. The data storage device of claim 3 , wherein the electronic processor is further configured to:

determine, in response to determining that the block is the open block, whether the data to be read is within the last coded word line of the block,

determine, in response to determining that the data to be read is not within the last coded word line of the block, the last coded word line of the block, and

set the flag indicative of the last coded word line of the block.

5. A data storage device, comprising:

a memory interface configured to interface with a non-volatile memory; and

an electronic processor configured to:

receive a read command to read data stored in a block of the non-volatile memory,

determine a last coded word line of the block,

set a flag indicative of the last coded word line that is determined,

determine whether the last coded word line is less than or equal to a word line threshold by comparing the last coded word line to the word line threshold,

set, in response to determining that the last coded word line is less than or equal to the word line threshold, the flag indicative of the last coded word line to a first value, and

set, in response to determining that the last coded word line is greater than the word line threshold, the flag indicative of the last coded word line to a second value.

6. The data storage device of claim 1 , wherein the flag is a two-bit flag.

7. The data storage device of claim 1 , wherein the read threshold offset value is determined based on the set flag and an age of a respective NAND cell.

8. A method comprising:

receiving a read command to read data stored in a block of a non-volatile memory,

determining a last coded word line of the block,

setting a flag indicative of the last coded word line that is determined,

determining a read threshold offset value based on the last coded word line of the block, and

performing the read command using the read threshold offset value that is determined.

9. The method of claim 8 , further comprising:

setting the flag indicative of the last coded word line within a flash module descriptor.

10. The method of claim 8 , further comprising:

determining whether the block is an open block, and

performing, in response to determining that the block is not the open block, the read command.

11. The method of claim 10 , further comprising:

determining, in response to determining that the block is the open block, whether the data to be read is within the last coded word line of the block,

determining, in response to determining that the data to be read is not within the last coded word line of the block, the last coded word line of the block, and

setting the flag indicative of the last coded word line of the block.

12. The method of claim 10 , further comprising:

determining whether the last coded word line is less than or equal to a word line threshold by comparing the last coded word line to the word line threshold,

setting, in response to determining that the last coded word line is less than or equal to the word line threshold, the flag indicative of the last coded word line to a first value, and

setting, in response to determining that the last coded word line is greater than the word line threshold, the flag indicative of the last coded word line to a second value.

13. A memory device that supports setting a flash module flag, the memory device comprising:

a memory including at least one block for storing data, the block composed of a plurality of word lines; and

a controller configured to set a flag value based on a last coded word line storing data within the block,

wherein the controller is further configured to set a read threshold offset value based on the last coded word line of the block.

14. The memory device of claim 13 , wherein the controller is further configured to set the flag value indicative of the last coded word line within a flash module descriptor.

15. The memory device of claim 13 , wherein the controller is further configured to set the flag value when the block is an open block.

16. The memory device of claim 13 , wherein the flag value is a two-bit flag.

17. A memory device that supports setting a flash module flag, the memory device comprising:

a memory including at least one block for storing data, the block composed of a plurality of word lines; and

a controller configured to set a flag value based on a last coded word line storing data within the block,

wherein the controller is further configured to set the flag value based on determining the last word line storing data within the block is greater than a word line threshold.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 24, 2022
From: JIN, MING; SUN, YONGKE; GU, LANLAN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059999/0203 →
Continuity (1)
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