Programmable input/output (PIO) engine interface architecture with direct memory access (DMA) for multi-tagging scheme for storage devices
In general, techniques are described by which to provide an interface architecture for storage devices. A storage device comprising non-volatile memory, and a hardware controller may be configured to perform various aspects of the techniques. The hardware controller may be configured to read from or write to one or more data registers in a host device to provide a direct communication channel between each of one or more threads executed by one or more processors of the host device and the hardware controller. The hardware controller may further be configured to send a plurality of commands received from the direct communication channel into a hardware queue, and issue access requests based on the plurality of commands to read data from or write data to the non-volatile memory.
1. A storage device comprising:
non-volatile memory; and
a hard ware controller comprising a hardware programmed input/output (PIO) engine configured to perform a multi tagging scheme, a plurality of command and status registers, a hardware direct memory access (DMA) engine and an interface controller configured to:
read from or write to one or more data registers in a host device to provide a direct communication channel between each of one or more threads executed by one or more processors of the host device and the hardware controller;
store a plurality of commands received from the direct communication channel to a hardware queue; and
issue access requests based on the plurality of commands to read data from or write data to the non-volatile memory.
2. The storage device of claim 1 , wherein the hardware controller includes:
the hardware (PIO) engine configured to receive the plurality of commands via the direct communication channel; and
the hardware (DMA) engine configured to issue the access requests based on the plurality of commands to read the data from or write the data to the non-volatile memory and further configured to write the data read from the non-volatile memory to the host device or read the data from the host device to be written to the non-volatile memory.
3. The storage device of claim 1 , wherein the one or more data registers are allocated to each of the one or more threads by a driver executed by the host device to establish the direct communication channel between each of the one or more threads and the hardware controller.
4. The storage device of claim 1 , wherein the one or more processors comprise a central processing unit, a graphics processing unit, or both the central processing unit and the graphics processing unit.
5. A storage device comprising:
non-volatile memory; and
a hard ware controller configured to:
read from or write to one or more data registers in a host device to provide a direct communication channel between each of one or more threads executed by one or more processors of the host device and the hard ware controller;
store a plurality of commands received from the direct communication channel to a hardware queue; and
issue access requests based on the plurality of commands to read data from or write data to the non-volatile memory, wherein the hard ware controller includes:
a hardware programmed input/output (PIO) engine configured to receive the plurality of commands via the direct communication channel; and
a hardware (DMA) engine configured to issue the access requests based on the plurality of commands to read the data from or write the data to the non-volatile memory and further configured to write the data read from the non-volatile memory to the host device or read the data from the host device to be written to the non-volatile memory, wherein the hardware PIO engine is further configured to:
implement a multi-channel tagging scheme to assign a unique tag to each of the plurality of commands, the unique tag including a unique channel identifier and a sequence number; and
process the commands based on the unique tags to send the plurality of commands received from the direct communication channel to the hardware queue.
6. The storage device of claim 5 , wherein the hardware PIO engine is configured to implement the multi-channel tagging scheme locally with respect to each direct communication channel to avoid global synchronization and locks associated with a software request queue to be shared by the one or more threads.
7. A storage device comprising:
non-volatile memory; and
a hard ware controller configured to:
read from or write to one or more data registers in a host device to provide a direct communication channel between each of one or more threads executed by one or more processors of the host device and the hard ware controller;
store a plurality of commands received from the direct communication channel to a hardware queue; and
issue access requests based on the plurality of commands to read data from or write data to the non-volatile memory, wherein the one or more threads are each allocated a respective one of the direct communication channels without implementing a software request queue having locks and atomicity and which is to be shared by the one or more threads.
8. A method comprising:
reading from or writing to, by a hardware controller of a storage device, one or more data registers in a host device to provide a direct communication channel for each of a plurality of threads executed by one or more processors of the host device, each of the direct communication channels enables direct communication between the respective one of the plurality of threads and the hardware controller;
translating, by the hardware controller, a plurality of commands received for accessing a non-volatile memory wherein the controller is configured with a hardware programmed input/output (PIO) engine configured to perform a multi tagging scheme, a plurality of command and status registers, a hardware direct memory access (DMA) engine and an interface controller;
storing, by the hardware controller, a plurality of commands received from the direct communication channel to a hardware queue; and
issuing, by the hardware controller, access requests based on the plurality of commands to read data from or write data to non-volatile memory of the storage device.
9. The method of claim 8 , further comprising:
receiving, by the hardware (PIO) engine of the hardware controller, the plurality of commands via the direct communication channel; and
issuing, by the hardware (DMA) engine of the hardware controller, the access requests based on the plurality of commands to read the data from or write the data to the non-volatile memory;
writing, by the hardware (DMA) engine, the data read from the non-volatile memory to the host device or read the data from the host device to be written to the non-volatile memory.
10. The method of claim 8 , wherein the one or more data registers are allocated to each of the plurality of threads by a driver executed by the host device to establish the direct communication channel between each of the plurality of threads and the hardware controller.
11. A method comprising:
reading from or writing to, by a hardware controller of a storage device, one or more data registers in a host device to provide a direct communication channel for each of a plurality of threads executed by one or more processors of the host device, each of the direct communication channels enables direct communication between the respective one of the plurality of threads and the hardware controller;
storing, by the hardware controller, a plurality of commands received from the direct communication channel to a hardware queue;
issuing, by the hardware controller, access requests based on the plurality of commands to read data from or write data to non-volatile memory of the storage device,
receiving, by a hardware programmed input/output (PIO) engine of the hardware controller, the plurality of commands via the direct communication channel;
issuing, by a hardware (DMA) engine of the hardware engine, the access requests based on the plurality of commands to read the data from or write the data to the non-volatile memory;
writing, by the hardware DMA engine, the data read from the non-volatile memory to the host device or read the data from the host device to be written to the non-volatile memory,
implementing, by the hardware PIO engine, a multi-channel tagging scheme to assign a unique tag to each of the plurality of commands, the unique tag including a unique channel identifier and a sequence number; and
processing, by the hardware PIO engine, the commands based on the unique tags to send the plurality of commands received from the direct communication channel to the hardware queue.
12. The method of claim 11 , wherein implementing the multi-channel tagging scheme comprising implementing the multi-channel tagging locally with respect to each direct communication channel to avoid global synchronization and locks associated with a software request queue to be shared by the plurality of threads.
13. A method comprising:
reading from or writing to, by a hardware controller of a storage device, one or more data registers in a host device to provide a direct communication channel for each of a plurality of threads executed by one or more processors of the host device, each of the direct communication channels enables direct communication between the respective one of the plurality of threads and the hardware controller;
storing, by the hardware controller, a plurality of commands received from the direct communication channel to a hardware queue; and
issuing, by the hardware controller, access requests based on the plurality of commands to read data from or write data to non-volatile memory of the storage device, wherein each of the plurality of threads is allocated a respective one of the direct communication channels without implementing a software request queue having locks and atomicity and which is to be shared by the plurality of threads.
14. A host device communicatively coupled to a storage device, the host device comprising:
an application;
a user space library;
a device driver;
one or more data registers; and
one or more processors configured to:
allocate the one or more data registers for each of one or more threads to provide a direct communication channel between each of the one or more threads and a hardware controller of the storage device the controller comprising a hardware programmed input/output (PIO) engine configured to perform a multi tagging scheme, a plurality of command and status registers, a hardware direct memory access (DMA) engine and an interface controller; and
execute the one or more threads to send a plurality of commands directly to a hardware queue via the direct communication channel, and directly read data from or directly write data to, in response to sending the plurality of commands, non-volatile memory of the storage device via the direct communication channel.
15. The host device of claim 14 , further comprising a memory,
wherein the one or more processor are further configured to allocate one or more queues within the memory for each of the one or more threads to establish the direct communication channel, the one or more queues allocated in a userspace of the memory to facilitate reading of the data from or writing of data to the non-volatile memory.
16. The host device of claim 14 , wherein the one or more processors execute the one or more threads to send the plurality of commands via programmed input/output (PIO) interface of the direct communication channel, and directly read data from or directly write data to the non-volatile memory via a direct memory access (DMA) interface of the direct communication channel.
17. The host device of claim 14 , wherein the one or more processors execute a driver to allocate the one or more data registers to each of the one or more threads to establish the direct communication channel between each of the one or more threads and the hardware controller.
18. The host device of claim 14 , wherein the one or more processors comprise a central processing unit, a graphics processing unit or both the central processing unit and the graphics processing unit.
19. A host device communicatively coupled to a storage device, the host device comprising:
one or more data registers; and
one or more processors configured to:
allocate the one or more data registers for each of one or more threads to provide a direct communication channel between each of the one or more threads and a hardware controller of the storage device; and
execute the one or more threads to send a plurality of commands directly to a hardware queue via the direct communication channel, and directly read data from or directly write data to, in response to sending the plurality of commands, non-volatile memory of the storage device via the direct communication channel, wherein the one or more processors execute a driver to allocate each of the one or more threads a respective one of the direct communication channels without implementing a software request queue having locks and atomicity and which is to be shared by the one or more threads.
20. A method comprising:
allocating, by one or more processors of a host device, one or more data registers for each of a plurality of threads to provide a direct communication channel for each of the plurality of threads, each of the direct communication channels enables direct communication between the respective one of the plurality of threads and a hardware controller of a storage device wherein the controller comprising a hardware programmed input/output (PIO) engine configured to perform a multi tagging scheme, a plurality of command and status registers, a hardware direct memory access (DMA) engine and an interface controller; and
executing, by the one or more processors, the plurality of threads to send a plurality of commands directly to a hardware queue via the direct communication channel, and directly read data from or directly write data to, in response to sending the plurality of commands, non-volatile memory of the storage device via the direct communication channel.
21. The method of claim 20 , further comprising allocating one or more queues within the memory for each of the plurality of threads to establish the direct communication channel, the one or more queues allocated in a userspace of the memory to facilitate reading of the data from or writing of data to the non-volatile memory.
22. The method of claim 20 , wherein executing the plurality of threads comprises executing the plurality of threads to send the plurality of commands via a programmed input/output (PIO) interface of the direct communication channel, and directly read data from or directly write data to the non-volatile memory via a direct memory access (DMA) interface of the direct communication channel.
23. The method of claim 20 , further comprising executing, by the one or more processors, a driver to allocate the one or more data registers to each of the plurality of threads to establish the direct communication channel between each of the plurality of threads and the hardware controller.
24. The method of claim 20 , wherein the one or more processors comprise a central processing unit, a graphics processing unit or both the central processing unit and the graphics processing unit.
25. A method comprising:
allocating, by one or more processors of a host device, one or more data registers for each of a plurality of threads to provide a direct communication channel for each of the plurality of threads, each of the direct communication channels enables direct communication between the respective one of the plurality of threads and a hardware controller of a storage device; and
executing, by the one or more processors, the plurality of threads to send a plurality of commands directly to a hardware queue via the direct communication channel, and directly read data from or directly write data to, in response to sending the plurality of commands, non-volatile memory of the storage device via the direct communication channel, further comprising executing, by the one or more processors, a driver to allocate each of the plurality of threads a respective one of the direct communication channels without implementing a software request queue having locks and atomicity and which is to be shared by the plurality of threads.
26. A system comprising:
a storage device comprising:
non-volatile memory; and
a hardware controller comprising a hardware PIO engine configured to perform a multi tagging scheme, a plurality of command and status registers, a hardware DMA engine and an interface controller; and
a host device including:
one or more data registers; and
one or more processors configured to allocate the one or more data registers for each of one or more threads to provide a direct communication channel between each of the one or more threads and the hardware controller of the storage device; and
execute the one or more threads to send a plurality of commands directly to a hardware queue via the direct communication channel so as to directly read data from or directly write data to, in response to sending the plurality of commands, non-volatile memory of the storage device via the direct communication channel, wherein the hardware controller is configured to:
send the plurality of commands received from the direct communication channel into a hardware queue; and
issue access requests based on the plurality of commands to read the data from or write the data to the non-volatile memory.