IP Library Granted Patent US 8,433,858
Granted Patent B1
US 8,433,858 · App. 13/425,303 · Granted Apr 30, 2013

Multi-interface and multi-bus structured solid-state storage subsystem

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Quick Facts
Patent No.
US 8,433,858
App. No.
13/425,303
Granted
Apr 30, 2013
Kind
B1
Abstract

A solid-state storage subsystem, such as a non-volatile memory card or drive, includes multiple interfaces and a memory area storing information used by a data arbiter to prioritize data commands received through the interfaces. As one example, the information may store a priority ranking of multiple host systems that are connected to the solid-state storage subsystem, such that the data arbiter may process concurrently received data transfer commands serially according to their priority ranking. A host software component may be configured to store and modify the priority control information in solid-state storage subsystem's memory area.

Claims (39)

1. A method of handling multiple data storage requests performed by a storage subsystem, the method comprising:

receiving a first set of data storage commands for accessing a storage of the storage subsystem according to a first signal interface;

receiving a second set of data storage commands for accessing the storage of the storage subsystem according to a second signal interface;

accessing a priority parameter stored in the storage subsystem; and

processing the first set of data storage commands and the second set of data storage commands in accordance with the priority parameter,

wherein the first and second sets of data storage commands are received from two different host systems that are concurrently connected to the storage subsystem, the storage comprising a nonvolatile memory, and

wherein the priority parameter is configured to designate an order for processing the first set of data storage commands and the second set of data storage commands based on at least one of a first host providing the first set of data storage commands according to the first signal interface and a second host providing the second set of data storage commands according to the second signal interface, a first type of command associated with the first set of data storage commands and a second type of command associated with the second set of data storage commands, and a first set of data included in the first set of data storage commands and a second set of data included in the second set of data storage commands.

2. The method of claim 1 , wherein the priority parameter indicates that a priority of the first set of data storage commands is higher than a priority of the second set of data storage commands.

3. The method of claim 2 , wherein processing the first set of data storage commands and the second set of data storage commands comprises executing the first set of data storage commands before executing the second set of data storage commands.

4. The method of claim 3 , wherein executing the first set of data storage commands before executing the second set of data storage commands comprises storing a first set of data associated with the first set of data storage commands before storing a second set of data associated with the second set of data storage commands.

5. The method of claim 3 , wherein executing the first set of data storage commands before executing the second set of data storage commands comprises retrieving a first set of data associated with the first set of data storage commands before retrieving a second set of data associated with the second set of data storage commands.

6. The method of claim 1 , wherein the first signal interface is PCI Express signal interface.

7. The method of claim 1 , wherein:

receiving the first set of data storage commands comprises receiving the first set of data storage commands via a first connector associated with the first signal interface; and

receiving the second set of data storage commands comprises receiving the second set of data storage commands via a second connector associated with the second signal interface.

8. The method of claim 7 , wherein the first signal interface is a PATA signal interface and the first connector comprises one of: a PC Card connector, a SmartCard adapter, and a CompactFlash adapter.

9. The method of claim 7 , wherein:

the first and second signal interfaces correspond to different signal interfaces; and

the first and second connectors correspond to different types of connectors.

10. The method of claim 7 , wherein the first connector is a CompactFlash card connector.

11. The method of claim 10 , wherein the second connector comprises one of: a USB series A connector receptacle, a USB series B receptacle, a USB mini-A receptacle, a USB mini-B receptacle, and a Micro USB connector.

12. The method of claim 10 , wherein the second connector is a SATA connector.

13. The method of claim 10 , wherein the second connector comprises one of: a four-pin FireWire connector receptacle, a six-pin FireWire connector receptacle, and a nine-pin FireWire connector receptacle.

14. The method of claim 7 , wherein the first connector comprises one of: a Secure Digital adapter, a MultiMediaCard adapter, and a Memory Stick adapter.

15. The method of claim 14 , wherein the second connector comprises one of: a USB connector, a FireWire connector, and a SATA connector.

16. The method of claim 7 , further comprising:

receiving a third set of data storage commands according to a third signal interface; and

processing the first set of data storage commands, the second set of data storage commands, and the third set of data storage commands in accordance with the priority parameter.

17. The method of claim 16 , wherein:

the first set of data storage commands is associated with a first set of data, the second set of data storage commands is associated with a second set of data, and a third set of data storage commands is associated with a third set of data; and

processing the first set of data storage commands, the second set of data storage commands, and the third set of data storage commands comprises retrieving the first, second, and third sets of data according to relative priorities of the first, second, and third sets of data storage commands.

18. The method of claim 16 , wherein:

the first set of data storage commands is associated with a first set of data, the second set of data storage commands is associated with a second set of data, and a third set of data storage commands is associated with a third set of data; and

processing the first set of data storage commands, the second set of data storage commands, and the third set of data storage commands comprises storing the first, second, and third sets of data according to relative priorities of the first, second, and third sets of data storage commands.

19. The method of claim 16 , wherein receiving the third set of data storage commands comprises receiving the third set of data storage commands via a third connector associated with the third signal interface.

20. The method of claim 19 , wherein:

the first connector comprises a USB connector, the second connector comprises a FireWire connector, and the third connector comprises a card-type connector;

the first signal interface corresponds to a USB signal interface, the second signal interface corresponds to a FireWire signal interface, and the third signal interface corresponds to an IDE signal interface; and

the storage subsystem is configured to substantially adhere to a PC Card form factor.

Assignments (13)
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 038744 FRAME 0481 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0556 →
RELEASE OF SECURITY INTEREST Recorded Mar 5, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 045501/0714 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038722/0229 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038744/0281 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038744/0481 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2016
From: SILICONSYSTEMS, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 037936/0204 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 23, 2015
From: SILICONSYSTEMS, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 036872/0017 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 23, 2012
From: DIGGS, MARK S.; MERRY, DAVID E., JR.
To: SILICONSYSTEMS, INC.
Reel/Frame 028835/0925 →