Power reduction during open and erased block reads of memory based on the position of last written word line of a memory block
A data storage device including, in one implementation, a non-volatile memory and a controller. The non-volatile memory includes a memory block. The memory block includes a plurality of word lines that are written sequentially from a first end of the memory block to a second end of the memory block. The controller is coupled to the non-volatile memory. The controller is configured to determine a last written word line of the memory block. The controller is also configured to set a non-selected word line voltage based on the last written word line of the memory block. The controller is further configured to apply the non-selected word line voltage to non-selected word lines of the memory block.
1. A data storage device, comprising:
a NAND flash memory including a memory block, the memory block including a plurality of word lines that are written sequentially from a first end of the memory block to a second end of the memory block; and
a controller circuitry coupled to the NAND flash memory and configured to:
determine a last written word line of the memory block,
set a non-selected word line voltage based on a position of the last written word line between the first end and the second end of the memory block, and
control the non-selected word line voltage to be applied to non-selected word lines of the memory block.
2. The data storage device of claim 1 , wherein, to set the non- selected word line voltage based on the position of the last written word line of the memory block, the controller is further configured to:
set the non-selected word line voltage to a first predetermined voltage when the last written word line of the memory block is positioned between the second end of the memory block and a first predetermined word line of the memory block,
set the non-selected word line voltage to a second predetermined voltage when the last written word line of the memory block is positioned between the first predetermined word line of the memory block and a second predetermined word line of the memory block, and
set the non-selected word line voltage to a third predetermined voltage when the last written word line of the memory block is positioned between the second predetermined word line of the memory block and the first end of the memory block,
wherein the second predetermined voltage is less than the first predetermined voltage, and wherein the third predetermined voltage is less than the second predetermined voltage.
3. The data storage device of claim 1 2 , wherein the controller is further configured to cause a decrease of the non-selected word line voltage by a predetermined amount when a program-erase cycle count of the memory block is less than a threshold.
4. The data storage device of claim 1 2 , wherein the controller is further configured to cause a decrease of the non-selected word line voltage by a predetermined amount when a temperature of the memory block is greater than a threshold.
5. The data storage device of claim 1 , wherein, to set the non-selected word line voltage based on the position of the last written word line of the memory block, the controller is further configured to set the non-selected word line voltage based at least in part on a predetermined monotonic relationship between the non-selected word line voltage and the position of the last written word line of the memory block.
6. The data storage device of claim 1 , wherein the non-selected word line voltage is a non-selected programmed word line voltage, wherein the controller is further configured to:
control the non-selected programmed word line voltage to be applied to non-selected word lines of the memory block positioned between the first end of the memory block and the last written word line of the memory block, and
control a non-selected erased word line voltage to be applied to non-selected word lines of the memory block positioned between the last written word line of the memory block and the second end of the memory block,
wherein the non-selected erased word line voltage is less than the non-selected programmed word line voltage.
7. The data storage device of claim 6 , wherein the controller is further configured to set the non-selected erased word line voltage to a fixed predetermined voltage.
8. The data storage device of claim 1 ,
wherein the controller circuitry includes a memory interface, a processor, and a controller memory, the memory interface being connected to the NAND flash memory, the processor and the controller memory being connected to each other and to the memory interface; and
wherein the controller circuitry is configured to:
determine the last written word line of the memory block by accessing a last-written-word-line record stored in the controller memory or by querying the NAND flash memory through the memory interface; and
cause the non-selected word line voltage to be applied to non-selected word lines of the memory block by sending a control signal to the NAND flash memory through the memory interface or by directly applying the non-selected word line voltage to the non-selected word lines of the memory block.
9. A method performed by a controller coupled to a non-volatile memory, the method comprising:
determining a last written word line of a memory block included in the non-volatile memory, the memory block including a plurality of word lines that are written sequentially from a first end of the memory block to a second end of the memory block;
setting a non-selected word line voltage based on a position of the last written word line between the first end and the second end of the memory block; and
applying the non-selected word line voltage to non-selected word lines of the memory block.
10. The method of claim 9 , wherein said setting the non-selected word line voltage based on the position of the last written word line of the memory block includes:
setting the non-selected word line voltage to a first predetermined voltage when the last written word line of the memory block is positioned between the second end of the memory block and a first predetermined word line of the memory block,
setting the non-selected word line voltage to a second predetermined voltage when the last written word line of the memory block is positioned between the first predetermined word line of the memory block and a second predetermined word line of the memory block, and
setting the non-selected word line voltage to a third predetermined voltage when the last written word line of the memory block is positioned between the second predetermined word line of the memory block and the first end of the memory block,
wherein the second predetermined voltage is less than the first predetermined voltage, and wherein the third predetermined voltage is less than the second predetermined voltage.
11. The method of claim 9 , further comprising decreasing the non- selected word line voltage by a predetermined amount when a program-erase cycle count of the memory block is less than a threshold.
12. The method of claim 9 , further comprising decreasing the non- selected word line voltage by a predetermined amount when a temperature of the memory block is greater than a threshold.
13. The method of claim 9 , wherein said setting the non-selected word line voltage based on the position of the last written word line of the memory block further includes setting the non-selected word line voltage based at least in part on a predetermined monotonic relationship between the non-selected word line voltage and the position of the last written word line of the memory block.
14. The method of claim 9 , wherein the non-selected word line voltage is a non-selected programmed word line voltage, wherein the method further comprising:
applying the non-selected programmed word line voltage to non-selected word lines of the memory block positioned between the first end of the memory block and the last written word line of the memory block; and
applying a non-selected erased word line voltage to non-selected word lines of the memory block positioned between the last written word line of the memory block and the second end of the memory block,
wherein the non-selected erased word line voltage is less than the non-selected programmed word line voltage.
15. The method of claim 14 , wherein the non-selected erased word line voltage is a fixed predetermined voltage.
16. An apparatus, comprising:
means for determining a last written word line of a memory block included in a NAND flash memory, the memory block including a plurality of word lines that are written sequentially from a first end of the memory block to a second end of the memory block;
means for setting a non-selected word line voltage based on a position of the last written word line between the first end and the second end of the memory block; and
means for applying the non-selected word line voltage to non-selected word lines of the memory block.
17. The apparatus of claim 16 , wherein the means for the setting the non-selected word line voltage based on the position of the last written word line of the memory block is configured to:
set the non-selected word line voltage to a first predetermined voltage when the last written word line of the memory block is positioned between the second end of the memory block and a first predetermined word line of the memory block,
set the non-selected word line voltage to a second predetermined voltage when the last written word line of the memory block is positioned between the first predetermined word line of the memory block and a second predetermined word line of the memory block, and
set the non-selected word line voltage to a third predetermined voltage when the last written word line of the memory block is positioned between the second predetermined word line of the memory block and the first end of the memory block,
wherein the second predetermined voltage is less than the first predetermined voltage, and wherein the third predetermined voltage is less than the second predetermined voltage.
18. The apparatus of claim 16 , further comprising means for decreasing the non-selected word line voltage by a predetermined amount when a program- erase cycle count of the memory block is less than a threshold.
19. The apparatus of claim 16 , further comprising means for decreasing the non-selected word line voltage by a predetermined amount when a temperature of the memory block is greater than a threshold.
20. The apparatus of claim 16 , further comprising means for the setting the non-selected word line voltage based at least in part on a predetermined monotonic relationship between the non-selected word line voltage and the position of the last written word line of the memory block.
21. The apparatus of claim 16 , wherein the non-selected word line voltage is a non-selected programmed word line voltage, and wherein the apparatus further comprises:
means for applying the non-selected programmed word line voltage to non-selected word lines of the memory block positioned between the first end of the memory block and the last written word line of the memory block; and
means for applying a non-selected erased word line voltage to non-selected word lines of the memory block positioned between the last written word line of the memory block and the second end of the memory block, and
wherein the non-selected erased word line voltage is less than the non-selected programmed word line voltage.
22. The apparatus of claim 16 ,
wherein the apparatus comprises a controller including a memory interface, a processor, and a controller memory, the memory interface being connected to the NAND flash memory, the processor and the controller memory being connected to each other and to the memory interface;
wherein the means for determining is configured to determine the last written word line of the memory block by accessing a last-written-word-line record stored in the controller memory or by querying the NAND flash memory through the memory interface; and
wherein the means for applying the non-selected word line voltage is configured to cause the non-selected word line voltage to be applied to the non-selected word lines of the memory block by sending a control signal to the NAND flash memory through the memory interface or by directly applying the non-selected word line voltage to the non-selected word lines of the memory block.