IP Library Granted Patent US 10,025,712
Granted Patent B2
US 10,025,712 · App. 15/174,955 · Granted Jul 17, 2018

Power-safe data management system

Inventors: Lyndon S. Chiu (Irvine, CA); Frederick H. Adi (Costa Mesa, CA)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G06F12/0804G06F3/0619G06F3/0647G06F3/0659G06F3/0685G06F3/0689G06F11/1441G06F12/0246G06F2212/1032G06F2212/2022
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Quick Facts
Patent No.
US 10,025,712
App. No.
15/174,955
Granted
Jul 17, 2018
Kind
B2
Abstract

Embodiments of the invention include systems and methods for recovering the system status and maintaining drive coherency after an unexpected power loss. In particular, these systems and methods reduce overhead for maintaining drive coherency by providing for pre-allocation of groups of write addresses and recording the pre-allocated groups of addresses to the non-volatile memory. Write processes can write to the pre-allocated group of addresses while the next group of addresses are pre-allocated and recorded to non-volatile memory.

Claims (37)

1. A method comprising:

writing data for a first write process to a first superblock of addresses in non-volatile memory, the first superblock designated as a current superblock in a master record stored in volatile memory;

upon writing data to a last address of the first superblock, designating a second superblock of addresses in the non-volatile memory as the current superblock in the master record stored in the volatile memory, wherein the second superblock was designated as a next superblock in the master record prior to be designated as the current superblock;

initiating a flush of the master record from the volatile memory to the non-volatile memory after the second superblock has been designated as the current superblock in the master record, the flush comprising writing the master record to the non-volatile memory; and

writing data for the first write process to the second superblock of addresses prior to completing the write of the master record to the non-volatile memory.

2. The method of claim 1 , wherein initiating the flush of the master record comprises adding the master record to a write queue for writing to the non-volatile memory.

3. The method of claim 2 , wherein a depth of the write queue is less than a capacity of the second superblock.

4. The method of claim 1 , further comprising:

writing data for a second write process to a third superblock of addresses in the non-volatile memory, the third superblock designated as a current superblock for the second write process in the master record;

upon writing data to a last address of the third superblock, designating a fourth superblock of addresses in the non-volatile memory as the current superblock for the second write process in the master record stored in the volatile memory, wherein the fourth superblock was designated as a next superblock for the second write process in the master record prior to be designated as the current superblock;

initiating a flush of the master record from the volatile memory to the non-volatile memory after the fourth superblock has been designated as the current superblock for the second write process in the master record, the flush comprising writing the master record to the non-volatile memory; and

writing data for the second write process to the fourth superblock of addresses after completing the write of the master record to the non-volatile memory.

5. The method of claim 4 , wherein the first write process was initiated by a user data manager and the second write process was not initiated by the user data manager.

6. The method of claim 1 , further comprising:

designating the first superblock of addresses as a previous superblock in the master record; and

designating a third superblock of addresses in the non-volatile memory as the next superblock in the master record.

7. The method of claim 1 , wherein the non-volatile memory comprises a plurality of die, and wherein the first and second superblock of addresses each comprise as least one address associated with each of the plurality of die.

8. A storage system, comprising:

non-volatile memory;

volatile memory; and

a controller configured to:

write data for a first write process to a first superblock of addresses in the non-volatile memory, the first superblock designated as a current superblock in a master record stored in the volatile memory;

upon writing data to a last address of the first superblock, designate a second superblock of addresses in the non-volatile memory as the current superblock in the master record stored in the volatile memory, wherein the second superblock was designated as a next superblock in the master record prior to be designated as the current superblock;

initiate a flush of the master record from the volatile memory to the non-volatile memory after the second superblock has been designated as the current superblock in the master record, the flush comprising writing the master record to the non-volatile memory; and

write data for the first write process to the second superblock of addresses prior to completing the write of the master record to the non-volatile memory.

9. The storage system of claim 8 , wherein the controller is configured to initiate the flush of the master record by adding the master record to a write queue for writing to the non-volatile memory.

10. The storage system of claim 9 , wherein a depth of the write queue is less than a capacity of the second superblock.

11. The storage system of claim 8 , wherein the controller is further configured to:

write data for a second write process to a third superblock of addresses in the non-volatile memory, the third superblock designated as a current superblock for the second write process in the master record;

upon writing data to a last address of the third superblock, designate a fourth superblock of addresses in the non-volatile memory as the current superblock for the second write process in the master record stored in the volatile memory, wherein the fourth superblock was designated as a next superblock for the second write process in the master record prior to be designated as the current superblock;

initiate a flush of the master record from the volatile memory to the non-volatile memory after the fourth superblock has been designated as the current superblock for the second write process in the master record, the flush comprising writing the master record to the non-volatile memory; and

write data for the second write process to the fourth superblock of addresses after completing the write of the master record to the non-volatile memory.

12. The storage system of claim 11 , wherein the first write process was initiated by a user data manager and the second write process was not initiated by the user data manager.

13. The storage system of claim 8 , wherein the controller is further configured to:

designate the first superblock of addresses as a previous superblock in the master record; and

designate a third superblock of addresses in the non-volatile memory as the next superblock in the master record.

14. The storage system of claim 8 , wherein the non-volatile memory comprises a plurality of die, and wherein the first and second superblock of addresses each comprise as least one address associated with each of the plurality of die.

Assignments (10)
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: SANDISK TECHNOLOGIES, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 069168/0273 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 16, 2016
From: CHIU, LYNDON S.; ADI, FREDERICK H.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 039769/0730 →
Continuity (2)
Continuation 13073588 · Mar 28, 2011
Related Publication 20160357670A1 · Dec 8, 2016