Granted Patent B2

US 11,188,251 · App. 16/662,340 · Granted Nov 30, 2021

Inventors: Shay Benisty (Beer Sheva, IL); Leonid Minz (Beer Sheva, IL)

Assignee: Western Digital Technologies, Inc.

G06F3/0658G06F3/064G06F3/0619G06F3/0679G06F9/466G06F9/5061G06F11/10

Abstract

Claims (53)

1. A storage device, comprising:

a non-volatile memory;

a volatile memory; and

a controller comprising a memory, wherein the controller is configured to:

receive a host-write transaction directed to a memory space defined within the controller, wherein the host-write transaction includes a destination address;

classify the host-write transaction based on a type of the host-write transaction to generate a classified transaction;

generate parity data based on the classified transaction; and

store data associated with the host-write transaction and the parity data in a portion of the memory space in the controller,

wherein when the controller classifies the host-write transaction, the controller is configured to:

translate the host-write transaction from a first protocol to a Non-Volatile Memory Express (NVMe) protocol to generate an NVMe transaction;

determine a type of the NVMe transaction; and

determine a destination address based on the type of the NVMe transaction.

2. The storage device of claim 1 , wherein the portion of the memory space comprises:

a first partition for storing submission queue data;

a second partition for storing completion queue data;

a third partition for storing a pointer; and

a fourth partition for storing host data, wherein each of the partitions is associated with a respective block size.

3. The storage device of claim 2 , wherein when the controller generates the parity data, the controller is configured to:

determine the data associated with the host-write transaction is stored in the first partition; and

generate the parity data based on the block size associated with the first partition, wherein a size of the parity data corresponds to the block size associated with the first partition.

4. The storage device of claim 1 , wherein when the controller classifies the host-write transaction, the controller is configured to:

determine a destination address of the classified transaction; and

classify the host-write transaction based on the destination address.

5. The storage device of claim 1 , wherein when the controller generates the parity data, the controller is configured to:

determine an allocated block size associated with the destination address; and

generate the parity data based on the allocated block size, wherein the allocated block size varies based on the destination address.

6. A method of accessing a storage device, comprising:

receiving, by a controller of the storage device, a host-write transaction directed to a memory space defined within the controller;

classifying the host-write transaction based on a type of the host-write transaction to generate a classified transaction;

generating a parity data based on the classified transaction; and

storing data associated with the host-write transaction and the parity data in a memory of the controller,

wherein classifying the host-write transaction further comprises:

translating the host-write transaction from a first protocol to a Non-Volatile Memory Express (NVMe) protocol to generate the classified transaction,

wherein the data associated with the host-write transaction defines a type of data comprising at least one selected from the group consisting of: a submission queue data, a completion queue data, a pointer, and a host data.

7. The method of claim 6 , wherein classifying the host-write transaction further comprises:

determining a destination address of the classified transaction; and

classifying based on the destination address.

8. The method of claim 7 , wherein generating the parity data further comprises:

determining an allocated block size associated with the destination address; and

generating the parity data based on the allocated block size, wherein the allocated block size varies based on the destination address.

9. The method of claim 7 ,

wherein the destination address falls within a portion of the memory of the controller,

wherein the portion of the memory includes a first section and a second section,

wherein the first section stores pointers and the second section stores host data; and

wherein the first section is associated with a first size of parity data, and the second section is associated with a second size of parity data.

10. The method of claim 6 ,

wherein the memory of the controller defines a first partition storing submission queue data, a second partition storing completion queue data, a third partition storing pointers, and a fourth partition storing host data,

wherein the first, second, third, and fourth partitions comprise a portion of the memory of the controller and

wherein each of the partitions of the portion is associated with a respective error correction code size.

11. The method of claim 10 , further comprising:

storing the data associated with the host-write transaction in the portion of the memory based on the type of the data.

12. The method of claim 6 , wherein the memory of the controller is a dynamic random access memory.

13. The method of claim 6 , wherein the memory space is a controller memory buffer (CMB) or a persistent memory region (PMR).

Assignments (10)