Storage system and method for enabling host-driven regional performance in memory
View Patent ↗A storage system and method for enabling host-driven regional performance in memory are provided. In one embodiment, a method is provided comprising receiving a directive from a host device as to a preferred logical region of a non-volatile memory in a storage system; and based on the directive, modifying a caching policy specifying which pages of a logical-to-physical address map stored in the non-volatile memory are to be cached in a volatile memory of the storage system. Other embodiments are provided, such as modifying a garbage collection policy of the storage system based on information from the host device regarding a preferred logical region of the memory.
1. A method for enabling host-driven regional performance in memory, the method comprising:
performing the following in a storage system comprising a non-volatile memory and a volatile memory:
receiving a directive from a host device as to a preferred logical region of the non-volatile memory;
based on the directive, modifying a caching policy specifying which pages of a logical-to-physical address map stored in the non-volatile memory are to be cached in the volatile memory, wherein priority is given to pages of the logical-to-physical address map that cover the preferred logical region over other pages of the logical-to-physical address map;
caching, in the volatile memory, the pages of the logical-to-physical address map that cover the preferred logical region; and
preventing the pages of the logical-to-physical address map that cover the preferred logical region from being removed from the volatile memory until a different directive from the host device is received to set a new preferred logical region.
2. The method of claim 1 , wherein priority is given by caching only those pages of the logical-to-physical address map that cover the preferred logical region.
3. The method of claim 1 , wherein priority is given by caching more pages of the logical-to-physical address map that cover the preferred logical region than pages of the logical-to-physical address map that cover other logical regions.
4. The method of claim 1 , wherein the pages of the logical-to-physical address map that cover the preferred logical region are prevented from being removed from the volatile memory by avoiding, during a swap in/out process, evicting pages of the logical-to-physical address map that cover the preferred logical region.
5. The method of claim 1 , further comprising mapping the preferred logical region to one or more single level cell (SLC) blocks in the non-volatile memory.
6. The method of claim 1 , wherein the non-volatile memory comprises a three-dimensional memory.
7. A storage system comprising:
a non-volatile memory;
a volatile memory; and
a controller configured to:
receive an indication from a host as to a preferred logical region of the non-volatile memory;
based on the indication, change a caching policy specifying which pages of a logical-to-physical address map stored in the non-volatile memory are to be cached in the volatile memory, wherein priority is given to pages of the logical-to-physical address map that cover the preferred logical region over other pages of the logical-to-physical address map;
cache, in the volatile memory, the pages of the logical-to-physical address map that cover the preferred logical region; and
prevent the pages of the logical-to-physical address map that cover the preferred logical region from being removed from the volatile memory until a different indication is received from the host to set a new preferred logical region.
8. The storage system of claim 7 , wherein priority is given by caching only those pages of the logical-to-physical address map that cover the preferred logical region.
9. The storage system of claim 7 , wherein priority is given by caching more pages of the logical-to-physical address map that cover the preferred logical region than pages of the logical-to-physical address map that cover other logical regions.
10. The storage system of claim 7 , wherein the pages of the logical-to-physical address map that cover the preferred logical region are prevented from being removed from the volatile memory by avoiding, during a swap in/out process, evicting pages of the logical-to-physical address map that cover the preferred logical region.
11. The storage system of claim 7 , wherein the controller is further configured to map the preferred logical region to one or more single level cell (SLC) blocks in the non-volatile memory.
12. The storage system of claim 7 , wherein the non-volatile memory comprises a three-dimensional memory.
13. A storage system comprising:
a non-volatile memory;
a volatile memory;
means for receiving an instruction from a host device as to a preferred logical area of the non-volatile memory;
means for modifying, based on the instruction, a caching policy specifying which pages of a logical-to-physical address map stored in the non-volatile memory are to be cached in the volatile memory, wherein priority is given to pages of the logical-to-physical address map that cover the preferred logical area over other pages of the logical-to-physical address map;
means for caching, in the volatile memory, the pages of the logical-to-physical address map that cover the preferred logical area; and
means for preventing the pages of the logical-to-physical address map that cover the preferred logical area from being removed from the volatile memory until a different instruction is received from the host device to set a new preferred logical area.
14. The storage system of claim 13 , wherein priority is given by caching only those pages of the logical-to-physical address map that cover the preferred logical area.
15. The storage system of claim 13 , wherein priority is given by caching more pages of the logical-to-physical address map that cover the preferred logical area than pages of the logical-to-physical address map that cover other logical areas.
16. The storage system of claim 13 , wherein the pages of the logical-to-physical address map that cover the preferred logical area are prevented from being removed from the volatile memory by avoiding, during a swap in/out process, evicting pages of the logical-to-physical address map that cover the preferred logical area.
17. The storage system of claim 13 , further comprising means for mapping the preferred logical area to one or more single level cell (SLC) blocks in the non-volatile memory.
18. The storage system of claim 13 , wherein the non-volatile memory comprises a three-dimensional memory.
19. The storage system of claim 13 , wherein the means for receiving and the means for modifying comprise a controller.
20. The storage system of claim 13 , wherein the storage system is integrated in the host device.