Spin-orbit torque bit design for improved switching efficiency
View Patent ↗A method for a non-volatile memory cell; specifically, a spin orbit torque MRAM (SOT-MRAM) memory cell which reduces the current required to switch individual bits. The memory cell includes a first interconnect line having a first longitudinal axis, an elliptically shaped MTJ bit (“bit”) having a long axis, and a second interconnect line having a second longitudinal axis perpendicular to the first interconnect line. The bit includes a polarized free layer, a barrier layer, and a polarized reference layer with a magnetic moment pinned at an angle different from the long axis. By disposing the long axis at an angle relative to the first longitudinal axis and second longitudinal axis and the reference layer as described, and applying a voltage to the interconnect line, a non-zero equilibrium angle can be induced between the free layer and the spin current or the Rashba field resulting in more coherent switching dynamics.
1. A memory cell, comprising:
a first interconnect line having a first longitudinal axis;
a second interconnect line having a second longitudinal axis disposed perpendicular to the first interconnect line; and
an elliptically shaped bit having a long axis disposed between the first interconnect line and the second interconnect line, wherein the long axis is disposed at an angle relative to the first longitudinal axis and the second longitudinal axis, and wherein the elliptically shaped bit comprises:
a free layer;
a reference layer having a magnetic moment, wherein the magnetic moment is disposed at an angle different from the long axis; and
a barrier layer disposed between the free layer and the reference layer.
2. The memory cell of claim 1 , wherein the barrier layer comprises an oxide material, the oxide material comprising one or more of: magnesium oxide (MgO), hafnium oxide (HfO), and aluminum oxide (AlOx).
3. The memory cell of claim 1 , wherein the elliptically shaped bit is spin-hall-effect-based magnetoresistive random access memory.
4. The memory cell of claim 1 , wherein the elliptically shaped bit is Rashba-effect-based magnetoresistive random access memory.
5. The memory cell of claim 1 , wherein the free layer is coupled to the first interconnect line.
6. The memory cell of claim 1 , wherein the first interconnect line comprises one or more of Platinum (Pt), Tantalum (Ta), Tungsten (W), Hafnium (Hf), Iridium (Ir), Copper-Bismuth (CuBi), Copper-Iridium (CuIr), and Aluminum-Tungsten (AuW), and wherein the first interconnect line has a thickness of about 4 nm to 20 nm.
7. The memory cell of claim 1 , wherein the first interconnect line comprises one or more of copper and aluminum, and wherein the first interconnect line has a thickness of about 20 nm to 100 nm.
8. The memory cell of claim 1 , wherein the reference layer is coupled to the first interconnect line.
9. The memory cell of claim 1 , wherein the long axis is disposed at an angle between 5 degrees and 60 degrees from the first longitudinal axis.
10. A memory cell, comprising:
an interconnect line having a first longitudinal axis; and
an elliptically shaped bit coupled to the interconnect line, wherein the elliptically shaped bit has a long axis, the long axis disposed at an angle between about 5 degrees and about 60 degrees relative to the first longitudinal axis, and wherein the elliptically shaped bit comprises:
a free layer;
a reference layer having a magnetic moment; and
a barrier layer disposed between the free layer and the reference layer.
11. The memory cell of claim 10 , wherein the elliptically shaped bit further comprises a capping layer.
12. The memory cell of claim 10 , wherein the elliptically shaped bit further comprises a pinning layer.
13. The memory cell of claim 12 , wherein the pinning layer is an antiferromagnet (AFM).
14. The memory cell of claim 12 , wherein the pinning layer comprises one or more of Iridium-Manganese (IrMn), Platinum-Manganese (PtMn), Nickel-Manganese (NiMn), Nickel Oxide (NiO), and Iron-Manganese (FeMn).
15. The memory cell of claim 10 , wherein the reference layer is part of a synthetic antiferromagnet structure.
16. The memory cell of claim 15 , wherein the synthetic antiferromagnet structure comprises a first ferromagnet layer adjacent to the barrier layer, a second ferromagnet layer, and a ruthenium layer disposed between the first ferromagnet layer and the second ferromagnet layer, and wherein the reference layer is the first ferromagnet layer.
17. The memory cell of claim 10 , wherein the free layer is coupled to the interconnect line.
18. The memory cell of claim 10 , wherein the free layer is coupled to the individual contact.
19. The memory cell of claim 10 , wherein the individual contact comprises one or more of Platinum (Pt), Tantalum (Ta), Tungsten (W), Hafnium (Hf), Iridium (Ir), Copper-Bismuth (CuBi), Copper-Iridium (CuIr), and Aluminum-Tungsten (AuW), and wherein the individual contact has a thickness of about 4 nm to 20 nm.
20. A memory array, comprising:
a first interconnect line having a first longitudinal axis;
a second interconnect line having a second longitudinal axis perpendicular to the first interconnect line;
a third interconnect line having a third longitudinal axis parallel to the first interconnect line;
a first elliptically shaped bit having a first long axis disposed between the first interconnect line and the second interconnect line, wherein the first long axis is disposed at an angle relative to the first longitudinal axis and the second longitudinal axis, and wherein the first elliptically shaped bit comprises:
a first free layer;
a first reference layer having a first magnetic moment disposed at an angle different from the first long axis; and
a first barrier layer disposed between the first free layer and the first reference layer; and
a second elliptically shaped bit having a second long axis disposed between the second interconnect line and the third interconnect line, wherein the second long axis is disposed at an angle relative to the second longitudinal axis and the third longitudinal axis, and wherein the second elliptically shaped bit comprises:
a second free layer;
a second reference layer having a second magnetic moment disposed at an angle different from the second long axis; and
a second barrier layer disposed between the second free layer and the second reference layer.
21. The memory array of claim 20 , wherein the memory array is a spin-hall-effect-based magnetoresistive random access memory array.
22. The memory array of claim 20 , wherein the memory array is a Rashba-effect-based magnetoresistive random access memory array.
23. The memory array of claim 20 , wherein the first free layer is coupled to the first interconnect line.
24. The memory array of claim 23 , wherein the first interconnect line comprises one or more of Platinum (Pt), Tantalum (Ta), Tungsten (W), Hafnium (Hf), Iridium (Ir), Copper-Bismuth (CuBi), Copper-Iridium (CuIr), and Aluminum-Tungsten (AuW), and wherein the first interconnect line has a thickness of about 4 nm to 20 nm.