Memory write verification using temperature compensation
A device is disclosed that includes a data write engine configured to store data into a block of a memory. The device also includes a post-write read engine configured to adjust a read voltage responsive to an output of the temperature sensor and to read stored data from the block based on the adjusted read voltage to verify integrity of the data. The device also includes a block manager configured to initiate a corrective operation responsive to an error characteristic of the data read from the block.
1. A device comprising:
a memory;
a temperature sensor;
a data write engine configured to store data into a block of the memory;
a post-write read engine configured to adjust a read voltage responsive to an output of the temperature sensor and to read stored data from the block based on the adjusted read voltage to verify the data has been successfully stored in the block; and
a block manager configured to initiate a corrective operation responsive to an error characteristic of the data read from the block.
2. The device of claim 1 , further comprising a data structure accessible to the post-write read engine and including a first read voltage offset corresponding to a first temperature range.
3. The device of claim 2 , the first read voltage offset associated with a first storage state of a multiple bits-per-cell storage, and the data structure including a second read voltage offset corresponding to the first temperature range and associated with a second storage state of the multiple bits-per-cell storage.
4. The device of claim 3 , The data structure further including a third read voltage offset and a fourth read voltage offset corresponding to a second temperature range.
5. The device of claim 1 , further comprising an error correction coding (ECC) engine coupled to the post-write read engine, and wherein the error characteristic corresponds to an error metric of the data from the ECC engine exceeding a threshold.
6. The device of claim 5 , wherein the corrective operation includes marking the block as invalid and initiating storage of the data at another block.
7. The device of claim 5 , wherein the corrective operation includes setting an indicator to indicate that the block is not to be used for data storage.
8. The device of claim 5 , further comprising:
a controller that is coupled to the memory and that includes the data write engine, the post-write read engine, the ECC engine, and the block manager; and
a memory device that includes the memory and that further includes:
write circuitry responsive to a write instruction from the data write engine to store the data into the block; and
read circuitry responsive to a read instruction from the post-write read engine to read the data from the block.
9. The device of claim 1 , further comprising a memory device that includes the memory and that includes at least one of the data write engine or the post-write read engine.
10. A method of data storage and verification, the method comprising:
in a data storage device that includes a memory, performing:
storing data into a block of the memory;
performing a storage verification operation that includes:
setting a first read voltage at least partially based on a temperature of the memory; and
reading the data from the block using the first read voltage to determine whether the data was successfully stored in the block; and
selectively initiating a corrective operation responsive to an error characteristic of the data read from the block.
11. The method of claim 10 , wherein the error characteristic corresponds to error data associated with the data read from the block exceeding a threshold, and wherein the corrective operation includes storing the data into another block of the memory.
12. The method of claim 11 , wherein the corrective operation further includes setting an indicator to indicate that the block is not to be used for multi-level cell (MLC) data storage.
13. The method of claim 10 , further comprising:
receiving an indication of the temperature from a temperature sensor; and
retrieving a first read voltage offset corresponding to the temperature from a look-up table.
14. The method of claim 13 , wherein setting the first read voltage includes applying the first read voltage offset to a default value of the first read voltage.
15. The method of claim 10 , wherein performing the storage verification operation further includes setting a second read voltage at least partially based on the temperature, and wherein reading the data from the block uses the first read voltage and the second read voltage.
16. The method of claim 15 , wherein setting the first read voltage includes applying a positive offset to a default value of the first read voltage, and wherein setting the second read voltage includes applying a negative offset to a default value of the second read voltage.
17. An apparatus comprising:
means for storing data;
means for adjusting a read voltage based on a temperature of the means for storing;
means for reading the stored data from the means for storing based on the adjusted read voltage to verify the stored data has been successfully stored in the means for storing data; and
means for performing a corrective action responsive to non-integrity of the stored data.
18. The apparatus of claim 17 , further comprising means for storing a first read voltage offset and a second read voltage offset corresponding to a first temperature range.
19. The apparatus of claim 18 , wherein the first read voltage offset is a positive offset and the second read voltage offset is a negative offset.
20. The apparatus of claim 18 , further comprising means for generating error data corresponding to the data read from the means for storing.