IP Library Granted Patent US 11,334,256
Granted Patent B2
US 11,334,256 · App. 16/780,281 · Granted May 17, 2022

Storage system and method for boundary wordline data retention handling

Inventors: Sahil Sharma (San Jose, CA); Nian Niles Yang (Mountain View, CA); Phil Reusswig (Mountain View, CA); Rohit Sehgal (San Jose, CA); Piyush A. Dhotre (Bangalore, IN)
Assignee: Western Digital Technologies, Inc.
G06F3/0619G06F3/0653G06F3/0659G06F3/0679G06F11/0757G11C11/409G11C11/4085
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Quick Facts
Patent No.
US 11,334,256
App. No.
16/780,281
Granted
May 17, 2022
Kind
B2
Abstract

A storage system and method for boundary wordline data retention handling are provided. In one embodiment, the storage system includes a memory having a single-level cell (SLC) block and a multi-level cell (MLC) block. The system determines if the boundary wordline in the MLC block has a data retention problem (e.g., by determining how long it has been since the boundary wordline was programmed). To address the data retention problem, the storage system can copy data from a wordline in the SLC block that corresponds to the boundary wordline in the MLC block to a wordline in another SLC block prior to de-committing the data in the SLC block. Alternatively, the storage system can reprogram the data in the boundary wordline using a double fine programing technique.

Claims (46)

1. A storage system, comprising:

a memory comprising a first single-level cell (SLC) memory area, a second SLC memory area, and a multi-level cell (MLC) memory area; and

a controller configured to communicate with the memory and further configured to:

write data to both the first SLC memory area and the MLC memory area;

determine whether the controller is ready to de-commit the data from the first SLC memory area in response to a threshold number of wordlines in the MLC memory area finishing a multi-stage programming operation; and

in response to determining that the controller is ready to de-commit the data from the first SLC memory area:

determine whether an amount of time that has passed since a last-written wordline in the MLC memory area was written is longer than a threshold amount of time; and

in response to determining that the amount of time is longer than the threshold amount of time:

copy data from a wordline in the first SLC memory area that corresponds to the last-written wordline in the MLC memory area to a wordline in the second SLC memory area; and

update a mapping table to reflect the copy.

2. The storage system of claim 1 , wherein the controller is further configured to, in response to a command to read the MLC memory area:

read data from wordlines written prior to the last-written wordline in the MLC memory area; and

instead of reading the last-written wordline in the MLC memory area, read the data from the wordline in the second SLC memory area.

3. The storage system of claim 1 , wherein the controller is further configured to log an identification of the last-written wordline in the MLC memory area and a time when the last-written wordline was written.

4. The storage system of claim 3 , wherein the identification and time are logged in volatile memory in the storage system.

5. The storage system of claim 1 , wherein the controller is further configured to de-commit the data from the first SLC memory area.

6. The storage system of claim 1 , wherein the MLC memory area comprises a quad-level cell (QLC) memory area.

7. The storage system of claim 1 , wherein the memory comprises a three-dimensional memory.

8. The storage system of claim 1 , wherein the storage system is configured to be integrated in a host.

9. The storage system of claim 1 , wherein the storage system is configured to be removably connected with a host.

10. The storage system of claim 1 , wherein the controller is ready to de-commit the data after completing a rolling fold operation.

11. In a storage system including a memory comprising a single-level cell (SLC) block and a multi-level cell (MLC) block, a method comprising:

programming data to both the SLC block and the MLC block;

determining whether the storage system is ready to de-commit the data from the SLC block in response to a threshold number of wordlines in the MLC block finishing a multi-stage programming operation; and

in response to determining that the storage system is ready to de-commit the data from the SLC block:

determining whether a predetermined amount of time has passed since a boundary wordline in the MLC block was programmed; and

in response to determining that the predetermined amount of time has passed, re-programming the data in the boundary wordline in the MLC block.

12. The method of claim 11 , wherein the data is programmed in the boundary wordline in the MLC block using a fine programing technique, and wherein the data is re-programmed in the boundary wordline using a double fine programing technique.

13. The method of claim 11 , further comprising logging an identification of the boundary wordline in the MLC block and a time when the boundary wordline was written.

14. The method of claim 13 , wherein the identification and time are logged in volatile memory in the storage system.

15. The method of claim 11 , further comprising de-committing the data from the SLC block.

16. The method of claim 11 , wherein the MLC block comprises a quad-level cell (QLC) block.

17. The method of claim 11 , wherein the storage system is ready to de-commit the data after a rolling fold operation.

18. A storage system, comprising:

a memory comprising a first single-level cell (SLC) memory area, a second SLC memory area, and a multi-level cell (MLC) memory area;

means for writing data to both the first SLC memory area and the MLC memory area;

means for determining whether the storage system is ready to de-commit the data from the first SLC memory area in response to a threshold number of wordlines in the MLC memory area finishing a multi-stage programming operation; and

means for, in response to determining that the storage system is ready to de-commit the data from the first SLC memory area:

determining whether an amount of time that has passed since a last-written wordline in the MLC memory area was written is longer than a threshold amount of time; and

in response to determining that the amount of time is longer than the threshold amount of time:

copying data from a wordline in the first SLC memory area that corresponds to the last-written wordline in the MLC memory area to a wordline in the second SLC memory area; and

updating a mapping table to reflect the copy.

19. The storage system of claim 18 , further comprising means for re-programming the data in the last-written wordline in the MLC memory area.

20. The storage system of claim 19 , wherein the data is programmed in the last-written wordline in the MLC memory area using a fine programing technique, and wherein the data is re-programmed in the last-written wordline using a double fine programing technique.

21. The storage system of claim 18 , further comprising means for logging an identification of the last-written wordline in the MLC memory area and a time when the last-written wordline was written.

22. The storage system of claim 18 , wherein the storage system is ready to de commit the data from the SLC memory area after a rolling fold operation.

Assignments (10)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 053482 FRAME 0453 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0279 →
SECURITY INTEREST Recorded May 14, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053482/0453 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 3, 2020
From: SHARMA, SAHIL; YANG, NIAN NILES; REUSSWIG, PHIL; SEHGAL, ROHIT; DHOTRE, PIYUSH A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 051703/0001 →