Error location pointers for non volatile memory
View Patent ↗Embodiments of the present disclosure generally relate to an improved method and system for error correction in non-volatile memory cells. The method includes writing data to a first location in non-volatile memory from a block of user data stored in DRAM and verifying the written data matches the block of user data. If the written data fails verification, the method further includes writing an error location pointer indicative of one or more error locations in the first location to a second location in non-volatile memory. Writing the one or more error locations to the error location pointer includes verifying the written error location pointer matches an address of the one or more error locations in the first location to ensure integrity of the error location pointer. Use of the error location pointer results in non-volatile memory with increased data rate, decreased read latency and a low probability of data loss.
1. An error correction method for non-volatile memory, comprising:
writing data to a first location in the non-volatile memory from a block of user data stored in DRAM;
verifying that the written data matches the block of user data stored in DRAM; and
if the written data fails verification, writing an error location pointer indicative of one or more error locations in the first location to a second location in the non-volatile memory, wherein the writing of the one or more error locations to the second location includes verifying that the written error location pointer matches an address of the one or more error locations in the first location to ensure integrity of the error location pointer wherein verifying that the written error location pointer matches an address of the one or more error locations in the first location comprises a cyclic redundancy check.
2. The method of claim 1 , further comprising:
if the written error location pointer fails verification, using an error correction code to decode the error location pointer.
3. The method of claim 1 , wherein the one or more error locations in the first location are written to the error location pointer in the second location jointly.
4. The method of claim 1 , wherein the one or more error locations in the first location are written to the error location pointer in the second location individually.
5. The method of claim 4 , wherein verifying that the written error location pointer matches an address of the one or more error locations in the first location comprises a cyclic redundancy check.
6. The method of claim 4 , further comprising:
if the written error location pointer fails verification, using an error correction code to decode the error location pointer.
7. A non-transitory computer readable storage medium storing a program, which, when executed by a processor performs an operation for correcting errors in non-volatile memory, the operation comprising:
writing data to a first location in the non-volatile memory from a block of user data stored in DRAM;
verifying that the written data matches the block of user data stored in DRAM; and if the written data fails verification, writing an error location pointer indicative of one or more error locations in the first location to a second location in the non-volatile memory, wherein writing of the one or more error locations to the second location includes verifying that the written error location pointer matches an address of the one or more error locations in the first location to ensure integrity of the error location pointer wherein verifying that the written error location pointer matches an address of the one or more error locations in the first location comprises a cyclic redundancy check.
8. The non-transitory computer readable storage medium of claim 7 , further comprising:
if the written error location pointer fails verification, using an error correction code to decode the error location pointer.
9. The non-transitory computer readable storage medium of claim 7 , wherein the one or more error locations in the first location are written to the error location pointer in the second location jointly.
10. The non-transitory computer readable storage medium of claim 7 , wherein the one or more error locations in the first location are written to the error location pointer in the second location individually.
11. The non-transitory computer readable storage medium of claim 10 , wherein verifying that the written error location pointer matches an address of the one or more error locations in the first location comprises a cyclic redundancy check.
12. The non-transitory computer readable storage medium of claim 10 , further comprising:
if the written error location pointer fails verification, using an error correction code to decode the error location pointer.
13. A system, comprising:
a processor; and
a memory, wherein the memory includes an application program configured to perform an operation for correcting errors in non-volatile memory, the operation comprising:
writing data to a first location in the non-volatile memory from a block of user data stored in DRAM;
verifying that the written data matches the block of user data store in DRAM; and
if the written data fails verification, writing an error location pointer indicative of one or more error locations in the first location to a second location in the non-volatile memory, wherein writing of the one or more error locations to the second location includes verifying that the written error location pointer matches an address of the one or more error locations in the first location to ensure integrity of the error location pointer wherein verifying that the written error location pointer matches an address of the one or more error locations in the first location comprises a cyclic redundancy check.
14. The system of claim 13 , further comprising:
if the written error location pointer fails verification, using an error correction code to decode the error location pointer.
15. The system of claim 13 , wherein the one or more error locations in the first location are written to the error location pointer in the second location jointly.
16. The system of claim 13 , wherein the one or more error locations in the first location are written to the error location pointer in the second location individually.
17. The system of claim 16 , further comprising:
if the written error location pointer fails verification, using an error correction code to decode the error location pointer.