IP Library Granted Patent US 10,228,746
Granted Patent B1
US 10,228,746 · App. 15/832,528 · Granted Mar 12, 2019

Dynamic distributed power control circuits

Inventors: Voleti Siva Raghu Ram (Bangalore, IN); Bhavin Odedara (Bangalore, IN); Sitaram Banda (Bangalore, IN); Nitin Gupta (Bangalore, IN)
Assignee: Western Digital Technologies, Inc.
G06F1/3206G06F1/26G06F1/263G06F1/324G06F1/3212G06F1/3225
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Quick Facts
Patent No.
US 10,228,746
App. No.
15/832,528
Granted
Mar 12, 2019
Kind
B1
Abstract

An apparatus includes a circuit and a voltage regulator having a first output terminal that is coupled to provide electrical power to the circuit. The voltage regulator is configured to provide the electrical power in a supply voltage range. The voltage regulator has a second output terminal configured to provide an indicator of electrical current provided by the first output terminal for control of the circuit.

Claims (44)

1. An apparatus, comprising:

a circuit;

a voltage regulator having a first output terminal that is coupled to provide electrical power to the circuit, the voltage regulator configured to provide the electrical power in a supply voltage range, the voltage regulator having a second output terminal configured to provide an indicator of electrical current provided by the first output terminal for control of the circuit;

a temperature transducer;

a pattern storage circuit; and

a pattern detection circuit coupled to receive the indicator of electrical current from the voltage regulator and receive the temperature measurements from the temperature transducer, the pattern detection circuit configured to identify one or more patterns of electrical current and temperature and store the one or more patterns in the pattern storage circuit for controlling power consumption of the circuit.

2. The apparatus of claim 1 wherein the second output terminal is coupled to provide the indicator of electrical current to the circuit, the circuit has a power consumption that is controllable, and the circuit is configured to control the power consumption in response to the indicator of electrical current.

3. The apparatus of claim 1 wherein the second output terminal is coupled to provide the indicator of electrical current to a controller that is coupled to the circuit, the circuit has a power consumption that is controllable, and the controller is configured to control the power consumption of the circuit in response to the indicator of electrical current.

4. The apparatus of claim 3 wherein the controller is configured to control the power consumption of the circuit by modifying a frequency of a signal provided to the circuit.

5. The apparatus of claim 1 wherein the circuit and the voltage regulator are located on a substrate.

6. The apparatus of claim 1 wherein the circuit is located on a first substrate and the voltage regulator is located on a second substrate.

7. The apparatus of claim 1 wherein the circuit is a memory controller that is configured to limit consumption of electrical current provided by the first output terminal to less than a predetermined current limit.

8. The apparatus of claim 7 wherein the pattern detection circuit that is configured to detect a pattern of memory controller activity that is predictive of a temperature that exceeds a temperature limit, the memory controller configured to adjust memory controller activity to not exceed the temperature limit.

9. The apparatus of claim 7 further comprising a monolithically formed three dimensional non-volatile memory coupled to the memory controller.

10. The apparatus of claim 1 wherein the voltage regulator comprises a power transistor controlled according to a feedback signal and a sense transistor connected in parallel with the power transistor, the sense transistor controlled according to the feedback signal to provide a voltage to the second output terminal that varies with electrical current provided by the first output terminal.

11. The apparatus of claim 10 wherein an input voltage is coupled to a source terminal of the power transistor and a source terminal of the sense transistor, the feedback signal is coupled to a first input of an amplifier, a reference voltage is coupled to a second input of the amplifier, an output of the amplifier is coupled to a gate of the power transistor and a gate of the sense transistor, the first output terminal is connected to a drain terminal of the power transistor and the second output terminal is connected to a drain terminal of the sense transistor.

12. The apparatus of claim 1 further comprising an analog to digital converter coupled to the second output terminal to provide a digital indicator of electrical current provided by the first output terminal.

13. A method, comprising:

maintaining an electrical supply to a circuit in a supply voltage range;

sensing an electrical current of the electrical supply to the circuit;

generating an indicator of the electrical current of the electrical supply to the circuit;

managing operation of the circuit according to the indicator;

wherein the circuit is a controller and wherein managing operation of the controller according to the indicator includes reducing controller activity in response to the electrical current exceeding a current limit;

monitoring temperature;

identifying one or more patterns of electrical current consumption associated with temperatures above a temperature limit, including

recording electrical current consumption and temperature over a period of time to correlate temperatures above the temperature limit with the one or more patterns of electrical current consumption by the controller;

recording the one or more patterns of electrical current consumption as associated with temperatures above the temperature limit;

monitoring electrical current consumption to detect a pattern that matches the one or more patterns of electrical current consumption by the controller; and

reducing controller activity in response to a pattern of electrical current consumption associated with a temperature above the temperature limit.

14. The method of claim 13 further comprising:

sensing one or more additional electrical currents provided to one or more additional circuits;

generating one or more additional indicators of the one or more additional electrical currents provided to the one or more additional circuits; and

managing operation of the circuit and the one or more additional circuits according to the indicator and the one or more additional indicators.

15. The method of claim 14 further comprising:

measuring a temperature associated with the circuit and the one or more additional circuits;

in response to the temperature exceeding a threshold temperature, identifying a power aggressor from among the circuit and the one or more additional circuits; and

reducing power consumption by the power aggressor.

16. An apparatus, comprising:

means for regulating a voltage to a power consuming unit;

means for measuring a current provided to the power consuming unit and generating an indicator of the current provided to the power consuming unit;

means for measuring a temperature;

means for managing power consumption by the power consuming unit in response to the indicator of the current and the temperature;

means for recording current and temperature data; and

means for identifying one or more patterns of measured current associated with a high temperature from recorded current and temperature data.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2017
From: RAM, VOLETI SIVA RAGHU; ODEDARA, BHAVIN; BANDA, SITARAM; GUPTA, NITIN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 044313/0557 →
Cited By (1)
US 12,455,614