IP Library Granted Patent US 12,193,166
Granted Patent B2
US 12,193,166 · App. 17/719,815 · Granted Jan 7, 2025

Printed circuit board having a sacrificial pad to mitigate galvanic corrosion

Inventors: Songtao Lu (Shanghai, CN); Hsiang Ju Huang (Taichung, TW); Binbin Zheng (Shanghai, CN); Cheng-Hsiung Yang (Taiwan, TW); Chien-Te Chen (Taichung, TW)
Assignee: Sandisk Technologies, Inc.
H05K3/282H05K1/09H05K2203/0591
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Quick Facts
Patent No.
US 12,193,166
App. No.
17/719,815
Granted
Jan 7, 2025
Kind
B2
Abstract

In one example, the present application describes a Printed Circuit Board (PCB) that mitigates galvanic corrosion during an Organic Solderability Preservative (OSP) process used during fabrication of the PCB. The PCB includes a first metal pattern and a second metal pattern electrically coupled to each other, where the first and second metal patterns are different metals. The first metal pattern has a first area that is exposed by a solder mask layer, and the second metal pattern has a second area that is exposed by the solder mask area. A ratio of the first area to the second area is less than a threshold ratio to mitigate the galvanic corrosion of the second metal pattern exposed on the PCB during the OSP process.

Claims (27)

1. A Printed Circuit Board (PCB) that mitigates galvanic corrosion during an Organic Solderability Preservative (OSP) process used during fabrication of the PCB, comprising:

a first metal pattern and a second metal pattern electrically coupled to each other, wherein the first metal pattern and the second metal pattern comprise different metals;

wherein the first metal pattern has a first area that is exposed by a solder mask layer;

wherein the second metal pattern has a second area that is exposed by the solder mask layer; and

wherein a ratio of the first area to the second area is less than a threshold ratio to mitigate the galvanic corrosion of the second metal pattern exposed on the PCB during the OSP process.

2. The PCB of claim 1 , wherein at least a portion of the solder mask layer is removed from the second metal pattern to increase the second area, thereby reducing the ratio of the first area to the second area.

3. The PCB of claim 1 , further comprising:

an additional second metal pattern electrically coupled to the first metal pattern, wherein at least a portion of the solder mask layer is removed from the additional second metal pattern.

4. The PCB of claim 1 , wherein the first metal pattern comprises at least one of gold and an alloy of gold.

5. The PCB of claim 1 , wherein the second metal pattern comprises copper.

6. The PCB of claim 1 , wherein:

the first metal pattern comprises one or more gold fingers; and

the second metal pattern comprises one or more copper traces.

7. The PCB of claim 1 , wherein the ratio is at least 30:1.

8. A Printed Circuit Board (PCB) that mitigates galvanic corrosion of the PCB during an Organic Solderability Preservative (OSP) process, the PCB comprising:

an electrode including an anode and a cathode;

wherein the cathode has a first area that is exposed by a solder mask layer;

wherein the anode has a second area that is exposed by the solder mask layer;

wherein a ratio of the first area to the second area is less than a threshold ratio; and

wherein the second area is increased to mitigate the galvanic corrosion of the anode exposed on the PCB during the OSP process based on determining that the ratio is greater than the threshold ratio.

9. The PCB of claim 8 , wherein the electrode comprises dissimilar metals electrically coupled together.

10. The PCB of claim 9 , wherein the dissimilar metals comprise copper and at least one of gold and alloys of gold.

11. The PCB of claim 9 , wherein a portion of the solder mask layer is removed from the anode to increase the second area.

12. The PCB of claim 9 , further comprising:

an additional anode; and

wherein a portion of the solder mask layer is removed from the additional anode to adjust the ratio.

13. The PCB of claim 9 , wherein the ratio is at least 30:1.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 19, 2022
From: LU, SONGTAO; HUANG, HSIANG JU; ZHENG, BINBIN; YANG, CHENG-HSIUNG; CHEN, CHIEN-TE
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059636/0505 →
Continuity (1)
Related Publication 20230337372A1 · Oct 19, 2023
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