Methods and systems for implementing high speed serial interface bus having inhomogeneous lane bundles and encodings
View Patent ↗The present disclosure relates to methods and systems for implementing a high-speed serial bus with inhomogeneous lane bundles and encodings. A system for transmitting information can include a bus with a plurality of lanes and a host in communication with a target. The host can run an application that writes data to and reads data from storage. The host can assign a first plurality of lanes and a first encoding to a first bundle and assign a second plurality of lanes and a second encoding to a second bundle. The host can also evaluate a bandwidth requirement for the read and write instructions and evaluate a bus performance. The host can also regroup the first bundle or the second bundle based on bandwidth requirements and bus performance and can assign a third plurality of lanes and a third encoding to the at least one of the first bundle and the second bundle.
1. A system for transmitting information in a communications protocol, the system comprising:
a bus comprising a plurality of lanes that can be grouped in at least one bundle of lanes; and
a host in communication with a target via the bus, the host running an application that writes data to and reads data from a storage in communication with the target, the host configured to:
assign a first plurality of lanes and a first encoding to a first bundle having a first bandwidth;
assign at least one lane and a second encoding to a second bundle having a second bandwidth;
evaluate a bandwidth requirement for at least one of application read instructions and application write instructions;
evaluate a bus performance;
regrouping the first bundle based on the at least one of the bandwidth requirement and the bus performance; and
assign a third plurality of lanes and a third encoding to the regrouped first bundle based on at least one of the bandwidth requirement and the bus performance, wherein the first bundle and the second bundle are inhomogeneous.
2. The system of claim 1 , wherein the host is further configured to assign a fourth plurality of lanes and a fourth encoding to the second bundle based on at least one of the bandwidth requirement and the bus performance.
3. The system of claim 1 , wherein the host is further configured to power down the first bundle based on at least one of the bandwidth requirement and the bus performance.
4. The system of claim 1 , wherein the bus further comprises at least one control signal for controlling the first bundle and the second bundle.
5. The system of claim 1 , wherein a number of lanes in the first plurality of lanes is negotiated between the host and the target.
6. The system of claim 1 , wherein the bus performance is evaluated based on a bus utilization.
7. The system of claim 1 , wherein the second bundle is configured to communicate control signals.
8. The system of claim 1 , wherein at least one of a number of lanes in the first plurality, a symbol length, a bandwidth, an encoding, a cyclic redundancy check, and an error-correcting code of the first bundle can dynamically change during running of the application.
9. The system of claim 1 , wherein the first bundle comprises sixteen lanes and implements an 128b/130b encoding and the second bundle comprises one lane and implements an 8b/10b encoding.
10. The system of claim 1 , wherein the first bundle is a clock-data-recovery bundle and the second bundle is a source-synchronous bundle.
11. A method for transmitting information in a communications protocol, the method comprising:
providing a bus comprising a plurality of lanes that can be grouped in at least one bundle of lanes;
providing a host in communication with a target via the bus, the host running an application that writes data to and reads data from a storage in communication with the target;
assigning, by the host, a first plurality of lanes and a first encoding to a first bundle having a first bandwidth;
assigning, by the host, at least one lane and a second encoding to a second bundle having a second bandwidth;
evaluating, by the host, a bandwidth requirement for at least one of application read instructions and application write instructions;
evaluating, by the host, a bus performance;
regrouping the first bundle based on the at least one of the bandwidth requirement and the bus performance; and
assigning, by the host, a third plurality of lanes and a third encoding to the first bundle based on at least one of the bandwidth requirement and the bus performance wherein the first bundle and the second bundle are inhomogeneous.
12. The method of claim 11 , further comprising assigning, by the host, a fourth plurality of lanes and a fourth encoding to the second bundle based on at least one of the bandwidth requirement and the bus performance.
13. The method of claim 11 , further comprising powering down the first bundle based on at least one of the bandwidth requirement and the bus performance.
14. The method of claim 11 , wherein the bus further comprises at least one control signal for controlling the first bundle and the second bundle.
15. The method of claim 11 , further comprising negotiating a number of lanes in the first plurality of lanes between the host and the target.
16. The method of claim 11 , wherein the bus performance is evaluated based on a bus utilization.
17. The method of claim 11 , further comprising configuring the second bundle to communicate control signals.
18. The method of claim 11 , further comprising dynamically changing during running of the application at least one of a number of lanes in the first plurality, a symbol length, a bandwidth, an encoding, a cyclic redundancy check, and an error-correcting code of the first bundle.
19. The method of claim 11 , wherein the first bundle comprises sixteen lanes and implements an 128b/130b encoding and the second bundle comprises one lane and implements an 8b/10b encoding.
20. The method of claim 11 , wherein the first bundle is a clock-data-recovery bundle and the second bundle is a source-synchronous bundle.