Semiconductor device package with coupled substrates
A semiconductor device package includes a first substrate extending along a first central plane, and a second substrate electrically connected to the first substrate and extending along a second central plane that is substantially parallel with and offset from the first central plane of the first substrate. One or more capacitors are electrically and mechanically connected to the second substrate via one or more leads. All of the one or more capacitors are positioned at the second substrate. All of the capacitors being positioned at the second substrate, reduces the complexity of and time required to manufacture the semiconductor device package.
1 . A semiconductor device package comprising:
a first substrate having a top planar surface and a bottom planar surface substantially parallel to the top planar surface, the first substrate extending along a first central plane substantially parallel with the top and bottom planar surfaces and equidistant between the top and bottom planar surfaces;
a second substrate electrically connected to the first substrate, the second substrate having a top planar surface and a bottom planar surface substantially parallel to the top planar surface, the second substrate extending along a second central plane substantially parallel with the top and bottom planar surfaces of the second substrate and equidistant between the top and bottom planar surfaces, the second central plane being substantially parallel with and offset from the first central plane of the first substrate; and
one or more capacitors electrically and mechanically connected to the second substrate via one or more leads,
wherein all of the one or more capacitors are positioned at the second substrate,
wherein each of the one or more capacitors extends circumferentially around a respective capacitor central axis, and
wherein each capacitor central axis of each of the one or more capacitors is positioned between the first central plane of the first substrate and the second central plane of the second substrate.
2 . The semiconductor device package of claim 1 further comprising:
a housing substantially enclosing the first substrate, the second substrate, and the one or more capacitors, the semiconductor device package having a width, a length, and a thickness defined by an Enterprise and Data Center Standard Form Factor (EDSFF).
3 . The semiconductor device package of claim 2 , wherein the width of the semiconductor device package is about 38.4 millimeters, the length is about 318.75 millimeters, and the thickness defined by a top surface and bottom surface of the housing is about 9.55 millimeters.
4 . The semiconductor device package of claim 2 , wherein each of the one or more capacitors is at least 0.55 millimeters from the top surface and bottom surface of the housing.
5 . The semiconductor device package of claim 1 , wherein the first substrate does not include any capacitors directly coupled to the first substrate.
6 . The semiconductor package of claim 1 ,
wherein each capacitor central axis of each of the one or more capacitors is parallel with the first central plane of the first substrate.
7 . The semiconductor device package of claim 1 , wherein the second central plane intersects each of the one or more capacitors.
8 . The semiconductor device package of claim 1 , wherein the first substrate has a first length and the second substrate has a second length that is less than the first length.
9 . The semiconductor device package of claim 8 , wherein the first length of the first substrate is twice the second length of the second substrate.
10 . The semiconductor device package of claim 1 , wherein the first substrate has a first thickness and the second substrate has a second thickness that is less than the first thickness.
11 . The semiconductor device package of claim 1 , wherein the first substrate includes a number of layers that is between two to four times greater than a number of layers included in the second substrate.
12 . A semiconductor device package comprising:
one or more capacitors;
a controller and one or more NAND dies; and
a first PCB extending along a first central plane that is substantially parallel to and equidistant from a top surface and bottom surface of the first PCB and a second PCB extending along a second central plane that is substantially parallel to and equidistant from a top surface and bottom surface of the second PCB, the second PCB electrically connected to and offset from the first PCB, the second PCB being substantially parallel to the first PCB and extending outwardly therefrom,
wherein the controller and the one or more NAND dies are directly coupled to the first PCB,
wherein each of the one or more capacitors is directly coupled to the second PCB,
wherein each of the one or more capacitors extends circumferentially around a respective capacitor central axis, and
wherein each capacitor central axis of each of the one or more capacitors is positioned between the first central plane of the first PCB and the second central plane of the second PCB.
13 . The semiconductor device package of claim 12 , wherein there are no capacitors directly connected to the first PCB.
14 . The semiconductor device package of claim 12 , wherein the one or more capacitors are the only electrical components directly connected to the second substrate.
15 . The semiconductor device package of claim 12 further comprising:
a housing substantially enclosing the first PCB, second PCB, and the one or more capacitors, the semiconductor device package having a width, a length, and a thickness defined by an Enterprise and Data Center Standard Form Factor (EDSFF).
16 . The semiconductor device package of claim 15 , wherein the width of the semiconductor device package is about 38.4 millimeters, the length is about 318.75 millimeters, and the thickness defined by a top surface and bottom surface of the housing is about 9.55 millimeters.
17 . The semiconductor device package of claim 12 , wherein the first PCB has a length that is about twice the length of the second PCB.
18 . A semiconductor device package comprising:
a first substrate means for providing electrical communication to one or more electrical components coupled to the first substrate means, the first substrate means extending along a first central plane that is substantially parallel with a top planar surface and a bottom planar surface of the first substrate means and the first central plane is equidistant between the top and bottom planar surfaces of the first substrate means;
a second substrate means for providing electrical communication to one or more electrical components coupled to the second substrate means, the second substrate means electrically and mechanically coupled to the first substrate means, the second substrate means extending along a second central plane that is substantially parallel with a top planar surface and a bottom planar surface of the second substrate means and the second central plane is equidistant between the top and bottom planar surfaces of the second substrate means; and
one or more electrical storage means each for storing an amount of electrical charge, each of the one or more electrical storage means being electrically connected to the second substrate means by a respective electrical connection means,
wherein the first and second substrate means are substantially parallel to one another and offset from one another,
wherein all of the one or more electrical storage means are positioned at the second substrate,
wherein each of the one or more electrical storage means extend circumferentially around a respective central axis, and
wherein each central axis of each of the one or more electrical storage means is positioned between the first central plane of the first substrate means and the second central plane of the second substrate means.
19 . The semiconductor device package of claim 18 , wherein the one or more electrical storage means are the only electrical components directly connected to the second substrate means that are configured to store and electrical charge.
20 . The semiconductor device package of claim 18 further comprising:
a housing means for substantially enclosing the first substrate means, the second substrate means, and the one or more electrical storage means, the semiconductor device package having a length, width, and thickness as defined by an Enterprise and Data Center Standard Form Factor (EDSFF).