Storage biasing for solid state drive accelerators
In response to the problems and scenarios described above, Solid State Drive (SSD) devices with hardware accelerators and methods for apportioning storage resources in the SSD are disclosed. SSDs typically comprise an array of non-volatile memory devices and a controller which manages access to the memory devices. The controller may also comprise one or more accelerators to either improve the performance of the SSD itself or to offload specialized computation workloads of a host-computing device. Different accelerators may be dynamically assigned portions of the non-volatile memory array according to the type of data being accessed and/or the throughput required. Provision is also made for the data to be accessed directly by the accelerators bypassing the controller.
1. A device, comprising:
a processor;
a memory comprising a plurality of non-volatile NAND flash memory devices configured into a plurality of blocks;
a first accelerator
comprising a throughput and configured to directly access the memory bypassing the processor;
the processor configured to assigns a portion of the memory as a data structure to the first accelerator based on a throughput of the first accelerator;
the first accelerator operating upon data words of a first width in a first mode and operating upon data words of a second width in a second mode;
the second width greater than the first width;
the processor assigning a data structure to the first accelerator in the first mode, wherein:
the data structure is distributed over a first portion of the plurality of non-volatile memory devices;
the processor assigning a data structure to the first accelerator in the second mode, wherein the data structure is distributed over a second portion of the plurality of non-volatile memory devices; and
wherein the second portion is greater than the first portion.
2. The device of claim 1 , wherein the data structure is interleaved.
3. The device of claim 2 , wherein the data structure is interleaved to a particular degree determined by the processor.
4. The device of claim 3 , wherein the degree of interleaving is based on the first accelerator throughput.
5. The device of claim 3 , wherein:
the data structure comprises a portion of the plurality of memory blocks, and
the portion of the plurality of memory blocks is distributed over a plurality of the non-volatile memory devices.
6. The device of claim 3 , wherein:
the first accelerator operates upon data words of a particular width, and
the data structure is distributed over at least a portion of the plurality of non-volatile memory devices according to the width of the data words.
7. The device of claim 3 , further comprising at least one memory channel, wherein the processor assigns a portion of the memory channels to the first accelerator according to the first throughput.
8. The device of claim 1 , further comprising a second accelerator, wherein the second accelerator directly accesses the memory bypassing the processor.
9. The device of claim 8 , wherein:
the first accelerator has a first throughput,
the second accelerator has a second throughput,
the processor assigns a first data structure to the first accelerator according to the first accelerator throughput, and
the processor assigns a second data structure to the second accelerator according to the second accelerator throughput.
10. The device of claim 8 , wherein:
the first accelerator operates upon data words of a first width,
the second accelerator operates upon data words of a second width,
the processor assigns a first data structure to the first accelerator, wherein:
the first data structure is distributed over a first portion of the plurality of non-volatile memory devices, and
the processor assigns a second data structure to the second accelerator, wherein:
the second data structure is distributed over a second portion of the plurality of non-volatile memory devices.
11. The device of claim 9 , further comprising a plurality of memory channels, wherein:
the processor assigns a first portion of the memory channels to the first accelerator according to the first throughput, and
the processor assigns a second portion of the memory channels to the second accelerator according to the second throughput.
12. The device of claim 9 , further comprising at least one memory channel, wherein the first accelerator and the second accelerator share at least one memory channel.
13. A method of operating a device, the device comprising a processor, a non-volatile memory array, and an accelerator, wherein the accelerator is coupled to the non-volatile memory array bypassing the processor, the method comprising:
determining a first throughput of the accelerator in a first mode;
assigning a first portion of the non-volatile memory array to the accelerator according to the first throughput;
assigning a portion of the non-volatile memory array as a data structure to the first accelerator based on the throughput of the first accelerator;
operating upon data words of a first width in a first mode, and data words of a second width in a second mode using the first accelerator, wherein the second width is greater than the first width;
assigning a data structure to the first accelerator in the first mode, wherein the data structure is distributed over a first portion of the of non-volatile memory array;
assigning a data structure to the first accelerator in the second mode, wherein the data structure is distributed over a second portion of the plurality of non-volatile memory devices; and
wherein the second portion is greater than the first portion.
14. The method of claim 13 , further comprising:
ceasing the operation of the accelerator in the first mode;
releasing the assignment of the first portion of the non-volatile memory array;
determining a second throughput of the accelerator in a second mode;
assigning a second portion of the non-volatile memory array to the accelerator according to the second throughput, wherein the second portion of the non-volatile memory array is segmented; and
operating the accelerator in the second mode.
15. The method of claim 14 , wherein the first portion of the non-volatile memory array is segmented; and the second portion of the non-volatile memory array is segmented.