3D cross-point memory manufacturing process having limited lithography steps
The present disclosure generally relates to semiconductor manufactured memory devices and methods of manufacture thereof. More specifically, methods for forming a plurality of layers of a 3D cross-point memory array without the need for lithographic patterning at each layer are disclosed. The method includes depositing a patterned hard mask with a plurality of first trenches over a plurality of layers. Each of the plurality of first trenches is etched all the way through the plurality of layers. Then the hard mask is patterned with a plurality of second trenches, which runs orthogonal to the plurality of first trenches. Selective undercut etching is then used to remove each of the plurality of layers except the orthogonal metal layers from the plurality of second trenches, resulting in a 3D cross-point array with memory material only at the intersections of the orthogonal metal layers.
1. A memory device, comprising:
a plurality of layers, wherein the plurality of layers comprises:
a first metal layer comprising a first metal material;
a selector layer;
a memory element layer; and
a second metal layer having a first portion comprising a second metal material and a second portion comprising a third metal material;
a plurality of first trenches, wherein the plurality of first trenches extends through the plurality of layers, wherein each of the plurality of first trenches is filled with a first dielectric material, and wherein the second portion is disposed in each of the plurality of first trenches; and
a plurality of second trenches, wherein the plurality of second trenches extends through the selector layer, the memory element layer, and the second metal layer, and wherein the plurality of second trenches runs orthogonal to the plurality of first trenches.
2. The memory device of claim 1 , wherein the first metal material comprises tungsten.
3. The memory device of claim 1 , wherein the selector layer comprises an ovonic threshold switch material.
4. The memory device of claim 1 , wherein the second metal material and the third metal material comprise substantially a same metal material.
5. The memory device of claim 1 , wherein the second metal material comprises titanium nitride.
6. The memory device of claim 1 , wherein the second metal material is different from the third metal material.
7. The memory device of claim 1 , wherein the first metal material comprises a same metal as the second metal material.
8. The memory device of claim 1 , wherein one or more of the second metal material and the third metal material comprises one or more of tungsten nitride, tungsten, and titanium nitride.
9. The memory device of claim 1 , wherein a first wall and a second wall of each of the plurality of first trenches are linear and parallel, and wherein a width of each of the plurality of first trenches is consistent throughout a length of each of the plurality of first trenches.
10. The memory device of claim 9 , wherein a first wall and a second wall of each of the plurality of second trenches are non-linear, and wherein each of the plurality of second trenches has a first convex portion connected to a second convex portion by a rectangular portion.
11. A memory device, comprising:
a plurality of layers, wherein the plurality of layers comprises:
a first metal layer comprising a first metal material;
a selector layer;
a memory element layer; and
a second metal layer comprising a second metal material;
a plurality of first trenches extending through the plurality of layers;
a third metal material disposed within the first trenches, the third metal material having a top surface that is coplanar with a top surface of the second metal layer and a bottom surface that is coplanar with a bottom surface of the second metal layer; and
a plurality of second trenches, wherein the plurality of second trenches runs orthogonal to the plurality of first trenches.
12. The memory device of claim 11 , wherein the first metal material comprises tungsten.
13. The memory device of claim 11 , wherein the selector layer comprises an ovonic threshold switch material.
14. The memory device of claim 11 , wherein the second metal material and the third metal material comprise substantially a same metal material.
15. The memory device of claim 11 , wherein one or more of the second metal material and the third metal material comprises one or more of titanium nitride, tungsten nitride, and tungsten.
16. The memory device of claim 11 , wherein the second metal material and the third metal material comprise different metal materials.
17. The memory device of claim 11 , wherein a first wall and a second wall of each of the plurality of first trenches are linear and parallel, and wherein a width of each of the plurality of first trenches is consistent throughout a length of each of the plurality of first trenches.
18. The memory device of claim 17 , wherein a first wall and a second wall of each of the plurality of second trenches are non-linear, and wherein each of the plurality of second trenches has a first convex portion connected to a second convex portion by a rectangular portion.
19. A memory structure, comprising:
a first plurality of layers, comprising:
a first metal material layer,
a selector material layer, and
a memory element material layer;
a second metal material layer;
a first trench extending through the first plurality of layers and the second metal material layer;
a third metal material disposed within the first trench at the second metal material layer;
a dielectric material substantially filling the first trench at one or more of the first plurality of layers; and
a second trench extending through the selector material layer, the memory element material layer, and the second metal material layer.
20. The memory structure of claim 19 , wherein the third metal material and the second metal material layer comprise substantially a same metal material.