IP Library Granted Patent US 11,941,263
Granted Patent B2
US 11,941,263 · App. 17/734,398 · Granted Mar 26, 2024

Flash-translation-layer-aided power allocation in a data storage device

Inventors: Amit Sharma (Bengaluru, IN); Niranjana Bhatta (Bengaluru, IN); Abhinandan Venugopal (Bengaluru, IN)
Assignee: Western Digital Technologies, Inc.
G06F3/0625G06F3/0659G06F3/0679
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Quick Facts
Patent No.
US 11,941,263
App. No.
17/734,398
Granted
Mar 26, 2024
Kind
B2
Abstract

A data storage device having an FTL configured to award to some pending memory operations a higher priority compared to the priority given to those operations by a default scheduling scheme. Such awards of higher priority may be based on a policy directed, e.g., at maximizing the effective data throughput, balancing the data throughput and the input/output bus throughput, or other performance objective. In response to awards of higher priority, a power-management circuit of the data storage device may dynamically route a constrained power supply such that the storage dies corresponding to the higher-priority operations preferentially receive power allocation in the next time interval(s). The remainder of the power budget (if any) in those time intervals may be allocated in accordance with the default scheduling scheme. According to an embodiment, nonlimiting examples of higher-priority operations may include read-retry operations, read-scrub-based relocation, internal control operations, or other suitable higher-priority operations.

Claims (53)

1. A data storage device, comprising:

a first plurality of storage dies to store data;

a power-management circuit to connect a power supply to a second plurality of the storage dies, the second plurality being a subset of the first plurality and being dynamically changeable in time; and

a controller including firmware for a flash translation layer;

wherein the flash translation layer is configured to maintain a queue of pending operations for the first plurality of dies and is further configured to award, in a time interval, a higher priority to a first subset of the pending operations than to a different second subset of the pending operations, at least one operation of the first subset being in the queue behind at least one operation of the second subset; and

wherein, in response to the first subset being selected by the flash translation layer, the power-management circuit is configured, in the time interval, to include storage dies corresponding to the first subset into the second plurality of the storage dies.

2. The data storage device of claim 1 , wherein the flash translation layer is configured to award the higher priority to maximize, in a sequence of time intervals, a data throughput for the first plurality of dies.

3. The data storage device of claim 1 ,

wherein circuitry corresponding to the first plurality of storage dies is configured to perform in-storage computations; and

wherein the flash translation layer is configured to award the higher priority to realize, in a sequence of time intervals, a selected ratio of a data throughput on an input/output bus of the data storage device and a data throughput for the first plurality of dies.

4. The data storage device of claim 1 ,

wherein the at least one operation of the first subset includes a read-retry operation; and

wherein the at least one operation of the second subset includes a host read operation.

5. The data storage device of claim 1 ,

wherein the at least one operation of the first subset includes a read-scrub-based relocation; and

wherein the at least one operation of the second subset includes a host read operation.

6. The data storage device of claim 1 ,

wherein the at least one operation of the first subset includes an internal control operation; and

wherein the at least one operation of the second subset includes a host write operation.

7. The data storage device of claim 1 ,

wherein the first plurality of dies is connected to the controller using a plurality of flash-interface modules; and

wherein the first subset of the pending operations includes operations on storage dies corresponding to different ones of the flash-interface modules.

8. The data storage device of claim 1 , wherein the flash translation layer is configured to keep the at least one operation of the second subset in the queue in the time interval.

9. The data storage device of claim 1 , wherein, in any time interval, a number of storage dies in the second plurality of the storage dies does not exceed a fixed number.

10. A method performed by a data storage device, the method comprising:

maintaining a queue of pending operations for a first plurality of storage dies of the data storage device;

awarding, in a time interval, a higher priority to a first subset of the pending operations than to a different second subset of the pending operations, at least one operation of the first subset being in the queue behind at least one operation of the second subset; and

connecting a power supply to a second plurality of the storage dies, the second plurality being a subset of the first plurality and being dynamically changeable in time; and

wherein, in the time interval, the connecting comprises including storage dies corresponding to the first subset into the second plurality of the storage dies in response to the awarding.

11. The method of claim 10 , wherein the awarding comprises awarding the higher priority to maximize, in a sequence of time intervals, a data throughput for the first plurality of dies.

12. The method of claim 10 ,

wherein circuitry corresponding to the first plurality of storage dies is configured to perform in-storage computations; and

wherein the awarding comprises awarding the higher priority to realize, in a sequence of time intervals, a selected ratio of a data throughput on an input/output bus of the data storage device and a data throughput for the first plurality of dies.

13. The method of claim 10 ,

wherein the at least one operation of the first subset includes a read-retry operation; and

wherein the at least one operation of the second subset includes a host read operation.

14. The method of claim 10 ,

wherein the at least one operation of the first subset includes a read-scrub-based relocation; and

wherein the at least one operation of the second subset includes a host read operation.

15. The method of claim 10 ,

wherein the at least one operation of the first subset includes a control operation internal to the data storage device; and

wherein the at least one operation of the second subset includes a host write operation.

16. The method of claim 10 ,

wherein the first plurality of dies is connected to a controller of the data storage device using a plurality of flash-interface modules; and

wherein the first subset of the pending operations includes operations on storage dies corresponding to different ones of the flash-interface modules.

17. The method of claim 10 , further comprising keeping the at least one operation of the second subset in the queue in the time interval.

18. The method of claim 10 , wherein, in any time interval, a number of storage dies in the second plurality of the storage dies does not exceed a fixed number.

19. The method of claim 10 , further comprising receiving the power supply from a host device connected to the data storage device.

20. An apparatus, comprising:

means for maintaining a queue of pending operations for a first plurality of dies of the data storage device;

means for awarding, in a time interval, a higher priority to a first subset of the pending operations than to a different second subset of the pending operations, at least one operation of the first subset being in the queue behind at least one operation of the second subset; and

means for connecting a power supply to a second plurality of the storage dies, the second plurality being a subset of the first plurality and being dynamically changeable in time; and

wherein, in the time interval, the means for connecting is configured to include storage dies corresponding to the first subset into the second plurality of the storage dies in response to the awarding.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 2, 2022
From: SHARMA, AMIT; BHATTA, NIRANJANA; VENUGOPAL, ABHINANDAN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059780/0970 →
Continuity (1)
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