IP Library Granted Patent US 10,916,306
Granted Patent B2
US 10,916,306 · App. 16/295,969 · Granted Feb 9, 2021

Burst mode operation conditioning for a memory device

Inventors: Alex Bazarsky (Holon, IL); Idan Alrod (Kfar Saba, IL); Eran Sharon (Rishon Lezion, IL); Ariel Navon (Revava, IL); Chris Petti (Mountain View, CA)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G11C13/0069G06F3/0604G06F3/0644G06F3/0679G11C13/0004G11C13/0061
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Quick Facts
Patent No.
US 10,916,306
App. No.
16/295,969
Granted
Feb 9, 2021
Kind
B2
Abstract

A controller for a phase change memory forms a dedicated burst write partition in the phase change memory and initializes memory cells of the dedicated burst write partition to a SET state. Programming of selected memory cells in the dedicated burst write partition is carried out using only RESET pulses.

Claims (22)

1. A memory device comprising a memory controller configured to:

execute a background operation to prepare a dedicated burst write partition within a non-volatile memory;

dynamically set a size of the dedicated burst write partition based on expected foreground burst write operation activity for the memory device and a latency of the background operation;

wherein only a sub-region less than an entirety of the dedicated burst write partition is conditioned into a SET state during the background operation, based on a tradeoff of the latency of the background operation and a time and a capacity of the non-volatile memory available to carry out the foreground burst write operation activity; and

in response to the foreground burst write activity apply only state change pulses for a RESET state to program the sub-region of the dedicated burst write partition with data of the foreground burst write activity.

2. The memory device of claim 1 , wherein the non-volatile memory is a phase change memory.

3. The memory device of claim 1 , the controller further configured to identify a subset of memory cells of the dedicated burst write partition based on the data of the foreground burst write activity.

4. A memory device comprising:

a non-volatile memory; and

a controller configured to:

prepare a dedicated burst write partition in the non-volatile memory;

dynamically set a size of the dedicated burst write partition based on expected burst write operation activity for the memory device and a latency of preparing the dedicated burst write partition;

condition only a sub-region less than an entirety of the dedicated burst write partition into a SET state based on a tradeoff of the latency and a time and a capacity of the non-volatile memory available to carry out the burst write operation activity; and

in response to the burst write operation activity apply only state change pulses for a RESET state to program the sub-region of the dedicated burst write partition with data of the burst write operation activity.

5. The memory device of claim 4 , the controller configured to execute a foreground operation to direct the burst write operation activity to the sub-region of the dedicated burst write partition.

6. A method comprising:

preparing a dedicated burst write partition in a phase change memory with a background operation of a memory device controller using only SET pulses;

wherein a size of the dedicated burst write partition is dynamically set during the background operation based on expected burst write activity and a latency of the background operation, and only a sub-region less than an entirety of the dedicated burst write partition is prepared with the SET pulses based on a tradeoff of the latency and a time and capacity of the phase change memory available to carry out the burst write activity; and

in response to a foreground burst write operation, apply only state change pulses for a RESET state to program the sub-region of the dedicated burst write partition with data of the burst write activity.

7. The method of claim 6 , further comprising:

analyzing the burst write operation to identify a subset of memory cells of the dedicated burst write partition to which to apply the RESET pulses.

8. The memory device of claim 4 , the controller further configured to execute a background operation to dynamically set the size of the dedicated burst write partition and to condition only the sub-region into the SET state.

Assignments (11)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2019
From: PETTI, CHRIS
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 049809/0882 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2019
From: BAZARSKY, ALEX; ALROD, IDAN; SHARON, ERAN; NAVON, ARIEL
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 049576/0139 →