IP Library Granted Patent US 12,593,406
Granted Patent B2
US 12,593,406 · App. 18/438,059 · Granted Mar 31, 2026

Printed circuit board having lead pads that accommodate offset electronic component leads

Inventors: Choong Keat Loh (Georgetown, MY); Chii Jian Saw (Bayan Lepas, MY); Chun Yan Koay (Seberang Perai, MY); Soon Chai Tee (Bayan Lepas, MY)
Assignee: Sandisk Technologies, Inc.
H05K1/119H05K1/182H05K2201/09072H05K2201/09381H05K2201/09427H05K2201/0949H05K2201/10015H05K2201/10757
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,593,406
App. No.
18/438,059
Granted
Mar 31, 2026
Kind
B2
Abstract

A printed circuit board (PCB) includes lead pads that are shaped and sized to account for offset leads of an electronic component, such as a capacitor. A proximal end of the lead pad has a first dimension and a distal end of the lead pad has a second dimension that is larger than the first dimension. The larger width of the proximal end of the lead pad accommodates offset leads and helps ensure lead joint integrity. The narrower width of the proximal end prevents solder from overflowing onto other areas on the PCB.

Claims (28)

1 . A printed circuit board (PCB) for a semiconductor package, comprising:

an opening defined in a planar surface of the PCB, the opening for receiving an electronic component; and

a plurality of lead pads proximate to the opening, each of the plurality of lead pads for receiving respective leads of the electronic component and having a first width at a proximal end and a second, larger width at a distal end.

2 . The PCB of claim 1 , further comprising a copper layer provided in each of the plurality of lead pads.

3 . The PCB of claim 1 , wherein the plurality of lead pads are shaped and spaced to accommodate the leads of the electronic component when the leads of the electronic component are separated by 5 millimeters (mm)+/−0.5 mm.

4 . The PCB of claim 1 , wherein the distal end of at least one of the plurality of lead pads is rounded.

5 . The PCB of claim 1 , wherein the first width of each of the plurality of lead pads is operable to prevent solder from overflowing from each of the plurality of lead pads and into the opening.

6 . The PCB of claim 1 , wherein the first dimension is between 0.85 millimeters (mm) and 0.95 mm.

7 . The PCB of claim 1 , wherein a width of each of the plurality of lead pads continuously increases between the first width and the second width.

8 . A semiconductor package, comprising:

a printed circuit board (PCB) defining an opening;

a first lead pad proximate the opening and having a proximal end and a distal end, the proximal end extending from the opening and having a first dimension and the distal end having a second dimension that is larger than the first dimension; and

a second lead pad proximate the opening and having a proximal end and a distal end, the proximal end extending from the opening and having the first dimension and the distal end having the second dimension.

9 . The semiconductor package of claim 8 , further comprising an electronic component provided in the opening, the electronic component including a first lead and a second lead, wherein the first lead is provided in the first lead pad and the second lead is provided in the second lead pad.

10 . The semiconductor package of claim 8 , wherein a shape of the first lead pad and the second lead pad is operable to receive offset leads of an electronic component when the electronic component is received within the opening.

11 . The semiconductor package of claim 10 , wherein the offset leads are separated by 5 millimeters (mm)+/−0.5 mm.

12 . The semiconductor package of claim 8 , further comprising a first copper layer provided in the first lead pad and a second copper layer provided in the second lead pad.

13 . The semiconductor package of claim 8 , wherein the distal end of the first lead pad is rounded.

14 . The semiconductor package of claim 8 , wherein the first dimension of the proximal end of the first lead pad controls solder overflow.

15 . The semiconductor package of claim 8 , wherein the first dimension is between 0.85 millimeters (mm) and 0.95 mm.

16 . A printed circuit board (PCB) for a semiconductor package, comprising:

an electronic component receiving means defined in a planar surface of the PCB;

a first electronic component lead receiving means proximate the electronic component receiving means, the first electronic component lead receiving means having a shape in which a proximal end of the first electronic component lead receiving means has a first width and a distal end of the first electronic component lead receiving means has a second width that is larger than the first width; and

a second electronic component lead receiving means proximate the electronic component receiving means, the second electronic component lead receiving means having a shape in which a proximal end of the second electronic component lead receiving means has the first width and a distal end of the second electronic component lead receiving means has the second width.

17 . The PCB of claim 16 , wherein the width of the first electronic component lead receiving means gradually increases between the proximal end and the distal end.

18 . The PCB of claim 16 , wherein the width of the proximal end of the first electronic component lead receiving means is adapted to control solder overflow between the first electronic component lead receiving means and the electronic component receiving means.

19 . The PCB of claim 16 , further comprising a first conductive layer in the first electronic component lead receiving means and a second conductive layer in the second electronic component lead receiving means.

20 . The PCB of claim 16 , wherein the distal end of the first electronic component lead receiving means is rounded.

Assignments (7)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT (AR) Recorded May 15, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 067417/0329 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 12, 2024
From: LOH, CHOONG KEAT; SAW, CHII JIAN; KOAY, CHUN YAN; TEE, SOON CHAI
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 066437/0381 →
Continuity (1)
Related Publication 20250261310A1 · Aug 14, 2025
References Cited (1)
US 20250194016A1 · Gangadharan · 2025 [cited by examiner]