IP Library Granted Patent US 11,481,271
Granted Patent B2
US 11,481,271 · App. 17/202,601 · Granted Oct 25, 2022

Storage system and method for using subcodes and convolutional-based LDPC interleaved coding schemes with read threshold calibration support

Inventors: Eran Sharon (Rishon Lezion, IL); Idan Goldenberg (Ramat Hasharon, IL); Idan Alrod (Herzeliya, IL); Ran Zamir (Ramat Gan, IL); Alexander Bazarsky (Holon, IL)
Assignee: Western Digital Technologies, Inc.
G06F11/1044G06F11/076G06F11/104G06F12/0882
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Quick Facts
Patent No.
US 11,481,271
App. No.
17/202,601
Granted
Oct 25, 2022
Kind
B2
Abstract

A storage system generates a low-density parity check (LDPC) code from a plurality of subcodes. The storage system stores each subcode in a different page of a word line in the memory. The subcode can be stored in one plane in the memory or across multiple planes. When the subcodes are stored across multiple planes, they can be stored in a checkboard pattern.

Claims (31)

1. A storage system comprising:

a memory; and

a controller coupled to the memory and configured to:

store each subcode of a plurality of subcodes in a different page of a word line in the memory; and

generate a low-density parity check (LDPC) code from the plurality of subcodes stored in the different pages of the word line in the memory.

2. The storage system of claim 1 , wherein the plurality of subcodes are stored in a same plane in the memory.

3. The storage system of claim 1 , wherein the plurality of subcodes are stored in different planes in the memory.

4. The storage system of claim 3 , wherein the plurality of subcodes are stored in a checkerboard pattern in the different planes in the memory.

5. The storage system of claim 1 , wherein the controller is further configured to calibrate a read threshold for a page of the memory.

6. The storage system of claim 5 , wherein the calibration is done using a subcode stored on the page being calibrated, and wherein the calibration is done based on subcode bits that are stored on the page and a set of parity check equations that involve solely the subcode bits.

7. The storage system of claim 5 , wherein the calibration is done using a histogram.

8. The storage system of claim 1 , wherein the controller is further configured to store interleaved codewords and non-interleaved codewords in the memory.

9. The storage system of claim 8 , wherein the interleaved codewords and the non-interleaved codewords are stored in different word lines, different word line zones, or different blocks in the memory.

10. The storage system of claim 8 , wherein the non-interleaved codewords are used for read threshold calibration.

11. The storage system of claim 1 , wherein the memory comprises a three-dimensional memory.

12. In a storage system comprising a memory, a method comprising:

generating a convolutional low-density parity check (CLDPC) code; and

storing different portions of the CLDPC code in different pages of a word line in the memory; and

storing interleaved codewords and non-interleaved codewords in the memory, wherein the interleaved codewords and the non-interleaved codewords are stored in different word lines, different word line zones, or different blocks in the memory.

13. The method of claim 12 , wherein the different portions of the CLDPC code are stored in a same plane in the memory.

14. The method of claim 12 , wherein the different portions of the CLDPC code are stored in different planes in the memory.

15. The method of claim 14 , wherein the different portions of the CLDPC code are stored in a checkerboard pattern in the different planes in the memory.

16. The method of claim 12 , further comprising calibrating a read threshold for a page of the memory based on a portion of CLDPC code bits that are stored on a calibrated page and based on a set of parity check equations that involve solely the portion of CLDPC code bits.

17. The method of claim 12 , further comprising calibrating a read threshold for a page of the memory using a histogram.

18. The method of claim 12 , wherein the memory comprises a three-dimensional memory.

19. A storage system comprising:

a memory;

means for storing each subcode of a plurality of subcodes in a different page of a word line in the memory; and

means for generating a low-density parity check (LDPC) code from the plurality of subcodes stored in the different pages of the word line in the memory.

20. The storage system of claim 19 , wherein the LDPC code is generated during encoding.

21. The storage system of claim 1 , wherein the LDPC code is generated during encoding.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 056285 FRAME 0292 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0001 →
SECURITY INTEREST Recorded May 19, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 056285/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 16, 2021
From: SHARON, ERAN; GOLDENBERG, IDAN; ALROD, IDAN; ZAMIR, RAN; BAZARSKY, ALEX
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 055604/0666 →