IP Library Granted Patent US 11,816,350
Granted Patent B2
US 11,816,350 · App. 17/878,589 · Granted Nov 14, 2023

Managing overwrite data within solid state drives

Inventor: Dinesh Kumar Agarwal (Bangalore, IN)
Assignee: Western Digital Technologies, Inc.
G06F3/0652G06F3/0665G06F3/0683G06F3/0604
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Quick Facts
Patent No.
US 11,816,350
App. No.
17/878,589
Granted
Nov 14, 2023
Kind
B2
Abstract

Storage devices can be configured to desirably reduce the number of times a zone reset or erasure occur via the use of one or more paired overwrite memory blocks. These storage devices can include a plurality of memory devices with some of these memory devices designated as overwrite memory devices. A controller within the storage device can be configured to direct the storage device to generate one or more subsets within the memory devices such as zones, pair each of subsets with at least one or more overwrite memory devices, store data sequentially within the subset of memory devices, and store any received overwrite data in the overwrite memory devices in chronological order. Data stored within the subsets of memory devices are not erased and instead of being overwritten directly, are instead pointed via a control table to a location in the overwrite memory devices storing the corresponding overwrite data.

Claims (46)

1. A storage device, comprising:

a plurality of memory devices, wherein one or more memory devices of the plurality of memory devices are designated as overwrite memory devices; and

a controller configured to direct the storage device to:

generate one or more subsets of the plurality of memory devices;

pair each of the one or more subsets of the plurality of memory devices with one or more overwrite memory devices;

in response to receiving an overwrite data from the storage device, store the overwrite data in the paired one or more overwrite memory devices in a chronological order;

update a control table indicative of a location of the overwrite data, wherein the control table is configured to associate the overwrite data with one or more corresponding virtually erased memory devices within the one or more subsets of the plurality of memory devices;

receive a reset command, the reset command indicative of a reset of the one or more subsets of the plurality of memory devices;

erase all data within the one or more subsets of the plurality of memory devices and the paired one or more overwrite memory devices; and

wherein a signal from a communicatively connected host computing device is formatted to indicate whether pairing between the one or more subsets of the plurality of memory devices and the paired one or more overwrite memory devices is required.

2. The storage device of claim 1 , further comprising on or more overprovisioned memory devices utilized to provide the paired one or more overwrite memory devices.

3. The storage device of claim 1 , wherein the control table is managed by a firmware operating within the storage device.

4. The storage device of claim 1 , wherein the control table is utilized to redirect requests for data within the virtually erased memory devices to the associated overwrite data within the paired one or more overwrite memory devices.

5. The storage device of claim 1 , wherein the virtually erased memory devices do not share adjacent logical block addresses.

6. The storage device of claim 1 , wherein the chronological order of the overwrite data associated with the erased memory devices is not in a sequential logical block address order.

7. The storage device of claim 1 , wherein the one or more subsets of the plurality of memory devices and the paired one or more overwrite memory devices are not erased until a reset command is issued.

8. The storage device of claim 7 , wherein the reset command erases all memory devices within the one or more subsets of the plurality of memory devices and the paired one or more overwrite memory devices.

9. The storage device of claim 1 , wherein the storage device is further configured to analyze read and write commands received.

10. The storage device of claim 1 , wherein the one or more subsets of the plurality of memory devices is a superblock of memory devices.

11. The storage device of claim 1 , wherein the paired one or more overwrite memory devices is a block of memory devices.

12. The storage devices of claim 1 , wherein there is one block of the paired one or more overwrite memory devices for every subset of ninety-six memory devices.

13. A method of managing overwrite data within a storage device comprising:

generating one or more subsets of the plurality of memory devices;

pairing each of the one or more subsets of the plurality of memory devices with one or more overwrite memory devices;

in response to receiving an overwrite data from the storage device, storing the overwrite data in the paired one or more overwrite memory devices in a chronological order; and

updating a control table to indicate a location of the overwrite data, wherein the control table is configured to associate the overwrite data with one or more corresponding virtually erased memory devices within the one or more subsets of the plurality of memory devices;

receiving a reset command, the reset command indicative of a reset of the one or more subsets of the plurality of memory devices;

erasing all data within the one or more subsets of the plurality of memory devices and the paired one or more overwrite memory devices; and

wherein a signal from a communicatively connected host computing device is formatted to indicate whether pairing between the one or more subsets of the plurality of memory devices and the paired one or more overwrite memory devices is required.

14. The method of claim 13 , wherein the control table is managed by a firmware operating within the storage device, and wherein the control table is utilized to redirect requests for data within the virtually erased memory devices to the associated overwrite data within the paired one or more overwrite memory devices.

15. The method of claim 13 , wherein the one or more subsets of the plurality of memory devices include a superblock of memory devices.

16. A storage device, comprising:

a firmware configured to receive commands from a communicatively coupled host computing device;

a plurality of memory devices, wherein one or more of the memory devices are designated as overwrite memory devices; and

a controller configured to receive commands from a communicatively coupled host computing device and direct the storage device to:

parse a received command to generate one or more zones within the memory devices;

generate one or more zones within the plurality of memory devices;

pair each of the one or more zones with at least one or more overwrite blocks of memory devices;

parse a received command to erase one or more memory devices within the zone;

virtually erase the one or more memory devices within the zone;

receive overwrite data directed to the one or more virtually erased memory devices;

store the overwrite data in the overwrite blocks in chronologically received order; and

update a control table indicative of a location of the received overwrite data, wherein the control table is configured to associate the received overwrite data with the one or more corresponding virtually erased memory devices within the zone;

receive a reset command, the reset command indicative of a reset of the one or more subsets of the plurality of memory devices;

erase all data within the one or more subsets of the plurality of memory devices and the one or more paired overwrite memory devices; and

format a signal from a communicatively connected host computing device to indicate whether pairing between the one or more subsets of the plurality of memory devices and the paired one or more overwrite memory devices is required.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2022
From: AGARWAL, DINESH KUMAR
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 060688/0402 →