IP Library Granted Patent US 11,284,502
Granted Patent B2
US 11,284,502 · App. 16/787,482 · Granted Mar 22, 2022

Thermal relief for through-hole and surface mounting

Inventors: Chun Sean Lau (Bayan Lepas, MY); Choon Kuai Lee (Bayan Lepas, MY); Ing Chyuan Ooi (Simpang Ampat, MY)
Assignee: Western Digital Technologies, Inc.
H05K1/0206H05K1/113H05K2201/062
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Quick Facts
Patent No.
US 11,284,502
App. No.
16/787,482
Filed
Feb 11, 2020
Granted
Mar 22, 2022
Kind
B2
Art Unit
2847
USPC
174/252
Abstract

A multi-layer printed circuit board (PCB) has a bonding surface disposed on a first surface and a first thermal relief pad disposed on the first surface and surrounding the bonding surface. A first conductive plane on the first surface partially surrounds the first thermal relief pad. The first conductive plane is connected to the bonding surface by one or more first spokes. A second thermal relief pad is disposed on the first surface and partially surrounds the first conductive plane. A second conductive plane is disposed on the first surface and surrounds the second thermal relief pad. The second conductive plane is connected to the first conductive plane by one or more second spokes. A through hole is located in the bonding surface for receiving an electrical connector of an electronic component.

Claims (42)

1. A multi-layer printed circuit board, comprising:

a first surface of the multilayer printed circuit board;

an electrically conductive bonding surface disposed on the first surface;

a first thermal relief pad disposed on the first surface and at least partially surrounding the electrically conductive bonding surface;

a first conductive plane disposed on the first surface and at least partially surrounding the first thermal relief pad;

at least one first spoke connecting the first conductive plane to the electrically conductive bonding surface, wherein the first spoke extends through the first thermal relief pad;

a second thermal relief pad disposed on the first surface and at least partially surrounding the first conductive plane and the first thermal relief pad;

a second conductive plane disposed on the first surface and at least partially surrounding the second thermal relief pad; and

at least one second spoke connecting the second conductive plane to the first conductive plane, wherein the second spoke extends through the second thermal relief pad;

wherein the second conductive plane includes at least one via extending from the second conductive plane into the printed circuit board to a metal layer, and

wherein a through-hole extends from the electrically conductive bonding surface through the multi-layer printed circuit board and perpendicular to the electrically conductive bonding surface.

2. The multi-layer printed circuit board of claim 1 , further comprising a thermal insulator disposed below the first surface and surrounding the through-hole.

3. The multi-layer printed circuit board of claim 2 , wherein the thermal insulator comprises insulating material that isolates metal traces from the through-hole.

4. The multi-layer printed circuit board of claim 1 , wherein the at least one first spoke is non-collinear with the at least one second spoke.

5. The multi-laver printed circuit board of claim 1 , wherein the at least one first and second spokes are generally rectangular.

6. The multi-layer printed circuit board of claim 5 , wherein the at least one second spoke has a greater surface area than the at least one first spoke.

7. The multi-layer printed circuit board of claim 6 , wherein a number and width of the at least one first spoke is determined based on a current requirement of an electronic component connected to the electrically conductive bonding surface.

8. The multi-layer printed circuit board of claim 7 , wherein a number and width of the at least one second spoke is determined based on the current requirement of the electronic component connected to the electrically conductive bonding surface.

9. The multi-layer printed circuit board of claim 1 , wherein the electrically conductive bonding surface and the metal layer are electrically connected by a path through the at least one first spoke, the at least one second spoke, and the at least one via.

10. The multi-layer printed circuit board of claim 1 , wherein areas of the first and second conductive planes are determined based on a current requirement of an electrical component connected to the electrically conductive bonding surface.

11. The multi-layer printed circuit board of claim 1 , wherein the electrically conductive bonding surface and the first thermal relief pad are curved.

12. The multi-layer printed circuit board of claim 1 , wherein the first surface is opposite a solder supply side of the multi-layer printed circuit board.

13. The multi-layer printed circuit board of claim 1 , wherein the first surface is top surface of the multi-layer printed circuit board.

14. A printed circuit board configured to manage temperature dependent soldering failures, the printed circuit board comprising:

a first surface of the multilayer printed circuit board;

a bonding surface means disposed on the first surface;

a first thermal relief pad means disposed on the first surface and partially surrounding the bonding surface means;

a first conductive plane means disposed on the first surface and partially surrounding the first thermal relief pad means, the first conductive plane means connected to the bonding surface means by at least one first spoke means;

a second thermal relief pad means disposed on the first surface and partially surrounding the first conductive plane means; and

a second conductive plane means disposed on the first surface and partially surrounding the second thermal relief pad means, the second conductive plane means connected to the first conductive plane means by at least one second spoke means which extends through the second thermal relief pad means;

wherein the second conductive plane means includes at least one via extending from the second conductive plane means into the printed circuit board to a metal layer, and

wherein a through-hole extends from the bonding surface means through the printed circuit board, thermal insulator means surrounding the through-hole and isolating the through hole from conductive planes within the printed circuit board.

15. The printed circuit board of claim 14 , wherein the at least one via extend from the second conductive plane means into the printed circuit board to the metal layer therein such that the bonding surface means and the metal layer are electrically connected.

16. In a multi-layer printed circuit board (PCB) comprising a first surface of the multilayer printed circuit board and an opposing second surface of the multilayer printed circuit board, and a thermal relief pad for managing heat generated by a soldering process, the thermal relief pad comprising:

an electrically conductive bonding pad formed on the first surface, wherein a through-hole is located within the electrically conductive bonding pad and extends from the first surface to the opposing second surface;

a first thermal plane disposed on the first surface and at least partially surrounding the electrically conductive bonding pad;

a first conductive plane disposed on the first surface and at least partially surrounding the first thermal plane;

at least one first spoke connecting the first conductive plane to the electrically conductive bonding pad, wherein the first spoke extends through the first thermal plane;

a second thermal plane disposed on the first surface and at least partially surrounding the first conductive plane;

a second conductive plane disposed on the first surface and at least partially surrounding the second thermal plane; and

at least one second spoke connecting the second conductive plane to the first conductive plane, wherein the second spoke extends through the second thermal plane, wherein one or more vias are disposed within the second conductive plane and extend from the second conductive plane to a conductive plane disposed within the multi-layer PCB,

wherein the multi-layer PCB further comprises a thermal insulator disposed below the first surface and surrounding the through-hole, wherein the thermal insulator isolates the through-hole from conductive planes disposed within the multi-layer PCB.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 053482 FRAME 0453 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0279 →
SECURITY INTEREST Recorded May 14, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053482/0453 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 18, 2020
From: LAU, CHUN SEAN; LEE, CHOON KUAI; OOI, ING CHYUAN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 051848/0874 →