Storage system and method for avoiding header to improve parity
A storage system stores data in a primary block and a copy of the data in a secondary block. Parity bits are stored with the data and the copy of the data. A header with logical block information is stored with the copy of the data in the secondary block. The data in the primary block is not stored with a header, which allows more parity bits to be stored with the data in the primary block. This provides more robust error protection for the data stored in the primary block and reduces the need to rely upon the copy of the data in the secondary block.
1. A storage system comprising:
a volatile memory;
a non-volatile memory; and
a controller coupled with the volatile memory and the non-volatile memory and configured to:
store data in a first data word in a primary block in the non-volatile memory;
store a copy of the data in a second data word in a secondary block in the non-volatile memory;
wherein:
the first and second data words are a same size but comprise a different number of parity bits;
the second data word comprises a header storing a logical address of the data; and
instead of comprising the header, the first data word comprises more parity bits than the second data word;
store, in the volatile memory, an association between the logical address of the data and a physical address of the primary block;
verify that the first data word was written correctly in the primary block; and
copy the association from the volatile memory to the non-volatile memory after verifying that the first data word was written correctly in the primary block.
2. The storage system of claim 1 , wherein the controller is further configured to in response to a power cycle occurring prior to the association being copied to the non-volatile memory:
read the logical address from the header of the second data word; and
re-store, in the volatile memory, the association between the logical address and the physical address of the primary block.
3. The storage system of claim 1 , wherein the controller is further configured to discard the second data word after verifying that the first data word was written correctly in the primary block.
4. The storage system of claim 1 , wherein the controller is further configured to use an enhanced post-write-read (EPWR) operation to verify that the first data word was written correctly in the primary block.
5. The storage system of claim 1 , wherein the controller is further configured to perform a low-density parity check (LDPC) operation using the parity bits.
6. The storage system of claim 1 , wherein the primary and secondary blocks comprise single-level cell (SLC) blocks or multi-level cell (MLC) blocks.
7. The storage system of claim 6 , wherein the controller is further configured to fold the data from the primary block to a multi-level cell (MLC) block.
8. The storage system of claim 1 , wherein the non-volatile memory comprises a three-dimensional memory.
9. In a storage system comprising a non-volatile memory, a method comprising:
creating a first data word comprising data and parity bits;
creating a second data word comprising the data, a header storing logical group information for the data, and parity bits, wherein there are fewer parity bits in the second data word than the first data word due to the header in the second data word;
writing the first data word in a primary block in the non-volatile memory;
writing the second data word in a secondary block in the non-volatile memory; and
verifying that the first data word was written correctly in the primary block; and
writing addressing information in the non-volatile memory after verifying that the first data word was written correctly in the primary block.
10. The method of claim 9 , wherein the first and second data words are a same size.
11. The method of claim 9 , further comprising:
in response to a power cycle occurring prior to writing the addressing information in the non-volatile memory, recreating the addressing information from the logical group information in the header of the second data word.
12. The method of claim 9 , further comprising discarding the second data word after verifying that the first data word was written correctly in the primary block.
13. The method of claim 12 , wherein the first data word is verified using an enhanced post-write-read (EPWR) operation.
14. The method of claim 9 , further comprising performing a low-density parity check (LDPC) operation using the parity bits.
15. The method of claim 9 , wherein the primary block comprises a single-level cell (SLC) block or a multi-level cell (MLC) block, and wherein the method further comprises folding the data from the primary block to a multi-level cell (MLC) block.
16. A storage system comprising:
a volatile memory;
a non-volatile memory;
means for storing data in a first data word in a primary block in the non-volatile memory; and
means for storing a copy of the data in a second data word in a secondary block in the non-volatile memory;
wherein:
the first and second data words are a same size but comprise a different number of parity bits;
the second data word comprises a header storing a logical address of the data; and
instead of comprising the header, the first data word comprises more parity bits than the second data word;
means for storing, in the volatile memory, an association between the logical address of the data and a physical address of the primary block;
means for verifying that the first data word was written correctly in the primary block; and
means for copying the association from the volatile memory to the non-volatile memory after verifying that the first data word was written correctly in the primary block.