IP Library Granted Patent US 10,579,611
Granted Patent B2
US 10,579,611 · App. 15/614,044 · Granted Mar 3, 2020

Selective event logging

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Quick Facts
Patent No.
US 10,579,611
App. No.
15/614,044
Granted
Mar 3, 2020
Kind
B2
Abstract

An apparatus includes one or more processors configured to execute instructions to generate a plurality of event results that includes a first event result and a second event result. The apparatus further includes a first buffer coupled to the one or more processors and a second buffer coupled to the first buffer. The first buffer is configured to store the plurality of event results. The apparatus further includes a circuit coupled to the first buffer. The first buffer is further configured to provide the first event result to the second buffer in response to detection by the circuit of a failure condition associated with the first event result.

Claims (38)

1. A data storage device comprising:

a non-volatile memory containing firmware of the data storage device;

one or more processors coupled to the non-volatile memory, the one or more processors configured to execute instructions of the firmware to generate a plurality of event results that includes a first event result and a second event result;

a first buffer coupled to the one or more processors and configured to store the plurality of event results;

a second buffer coupled to the first buffer; and

a circuit coupled to the first buffer,

wherein the first buffer is further configured to:

provide the first event result to the second buffer in response to detection by the circuit of a failure condition associated with the first event result, wherein detection of the failure condition includes finding the first event result in an event table; and

discard the second event result in response to detection by the circuit of a success condition associated with the second event result, wherein detection of the success condition includes failing to find the second event result in the event table, the success condition indicating successful execution of firmware instructions by the one or more processors.

2. The data storage device of claim 1 , wherein the circuit is further configured to determine that the first event result is to be provided to the second buffer based on a filtering policy that indicates a particular set of events to be provided to the second buffer.

3. The data storage device of claim 2 , wherein the circuit is further configured to determine that the second event result is excluded from the particular set of events.

4. The data storage device of claim 1 , wherein:

the first event result corresponds to a failed write operation in the non-volatile memory performed during execution of the firmware.

5. The data storage device of claim 4 , wherein the second event result corresponds to a successful write operation in the non-volatile memory performed during execution of the firmware.

6. The data storage device of claim 1 , further comprising an interface configured to receive the first event result from the second buffer.

7. The data storage device of claim 6 , wherein the interface is further configured to provide the first event result to an access device.

8. The data storage device of claim 6 , further comprising:

a controller that includes the one or more processors, the first buffer, the second buffer, the circuit, and the interface, wherein the interface is further configured to provide the first event result to the non-volatile memory.

9. A method comprising:

executing firmware instructions of a data storage device using one or more central processing units (CPUs) of the data storage device to generate a plurality of event results that includes a first event result and a second event result;

storing the plurality of event results at a memory of the data storage device;

in response to finding the first event result in an event table, maintaining the first event result at the memory; and

in response to failing to find the second event result in the event table, deleting the second event result from the memory.

10. The method of claim 9 , wherein:

the first event result corresponds to a failed operation performed during execution of the firmware.

11. The method of claim 10 , wherein the second event result corresponds to a successful operation performed during execution of the firmware.

12. The method of claim 9 , further comprising providing the first event result to an interface after deleting the second event result from the memory.

13. The method of claim 12 , further comprising providing the first event result from the interface to an access device.

14. The method of claim 12 , further comprising providing the first event result from the interface to a non-volatile memory.

15. The method of claim 9 , further comprising initiating a compaction process at the memory after deleting the second event result from a first address, the compaction process including copying a third event result to the first address.

16. The method of claim 15 , wherein the compaction process is performed as a background process.

17. The method of claim 9 , wherein a data capacity of the memory is based on a number of events indicated by the table.

18. An apparatus comprising:

means for executing data storage device firmware instructions to generate a plurality of event results that includes a first event result and a second event result;

means for storing the plurality of event results; and

means for accessing a table and for discarding the second event result from the means for storing based on the table indicating the second event result, the table indicating a set of successful events associated with successful execution of one or more of the data storage device instructions by the means for executing instructions.

19. The apparatus of claim 18 , further comprising means for providing the first event result to a non-volatile memory after discard of the second event result.

20. The apparatus of claim 18 , further comprising means for providing the first event result to an access device after discard of the second event result.

Assignments (10)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 5, 2017
From: TURGEMAN, AHIAD; BEN-RUBI, REFAEL; COHEN, MOSHE; SHIR, URI; BRIEF, DAVID CHAIM
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 042601/0643 →