IP Library Granted Patent US 10,740,178
Granted Patent B2
US 10,740,178 · App. 16/140,192 · Granted Aug 11, 2020

Self-prioritizing adaptive retry threshold adjustment

Inventor: Xiaoheng Chen (Dublin, CA)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G06F11/1068G06F11/141G06F11/1435G06F11/1471
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Quick Facts
Patent No.
US 10,740,178
App. No.
16/140,192
Granted
Aug 11, 2020
Kind
B2
Abstract

Exemplary methods and apparatus are provided for read recovery in solid state devices (SSDs) with non-volatile memories (NVMs). In some examples, a dynamic priority read retry table (PRT) is generated for use with a static read retry table (RRT). In one aspect, a most recent successful read retry entry is determined from among the entries in the RRT. The most recent successful read retry entry is inserted as a first priority read retry entry within the PRT. A subsequent read recovery operation is performed using the first priority read retry entry of the PRT. In some examples, one or more neighboring values are selected for each entry in the PRT starting with the newest entry and proceeding chronologically to the oldest entry. The use of the PRT may help address die-to-die variations, block-to-block variations, or the transient changes that may occur in device physics within NVMs.

Claims (44)

1. An apparatus, comprising:

a physical memory array; and

a processor configured to

perform a read recovery operation within the physical memory array using entries in a read retry table of set order,

determine a most recent successful read retry entry from among the entries in the read retry table,

generate a separate priority read retry table, and

insert the most recent successful read retry entry as a first priority entry in the priority read retry table for use during a subsequent read recovery operation.

2. The apparatus of claim 1 , further comprising a read recovery component configured to perform the read recovery operation within the physical memory array, wherein the read recovery component is configured to use the first priority entry within the priority read retry table as a first candidate read retry entry during the read recovery operation.

3. The apparatus of claim 1 , wherein the processor is further configured to repeatedly insert the most recent successful read retry entry as a new first priority entry in the priority read retry table for each successful read recovery.

4. The apparatus of claim 3 ,

wherein the priority read retry table is configured by the processor with a set size of a number of entries; and

wherein the processor is further configured to delete an oldest successful read retry entry from the priority read retry table if addition of a newest successful read retry entry causes the set size of the priority read retry table to be exceeded.

5. The apparatus of claim 1 , wherein the processor is further configured to select, during read recovery operations, the read retry entries to be tried for each read recovery operation according to a prescribed priority order until a successful read recovery is achieved.

6. The apparatus of claim 5 , wherein the processor is further configured to select entries in the priority read retry table for use in read recovery operations starting with the newest successful entry and proceeding chronologically to an oldest successful entry.

7. The apparatus of claim 6 , wherein the processor is further configured to select one or more neighboring values for each entry in the priority read retry table starting with the newest successful entry and proceeding chronologically to the oldest successful entry.

8. The apparatus of claim 7 , wherein the processor is further configured to select entries from the read retry table according to the set order of the read retry table.

9. The apparatus of claim 1 , wherein the processor is one or more of a non-volatile memory (NVM) controller, a solid state device (SSD) controller, and a host device processor.

10. A method for use with a physical memory array, the method comprising:

generating a read retry table having a set order;

generating a separate priority read retry table;

determining a most recent successful read retry entry from among the entries in the read retry table for a first read recovery operation on the physical memory array;

setting the most recent successful read retry entry as a first priority read retry entry within the priority read retry table; and

performing a second read recovery operation on the physical memory array using the first priority read retry entry of the priority read retry table.

11. The method of claim 10 , wherein the setting the most recent successful read retry entry as the first priority read retry entry within the priority read retry table is repeated for each successful read retry entry.

12. The method of claim 11 , wherein the priority read retry table has a maximum number of entries, and wherein the method further comprises deleting an oldest successful read retry entry from the priority read retry table if addition of a newest successful read retry entry causes the maximum number of entries to be exceeded.

13. The method of claim 10 , further comprising:

during the read recovery operation within the physical memory array, choosing read retry entries to be tried for additional read recovery operations according to a predetermined priority order until a successful read recovery is achieved.

14. The method of claim 13 , wherein the predetermined priority order comprises:

(1) selecting entries in the priority read retry table starting with a newest successful entry and proceeding chronologically to an oldest successful entry in the priority read retry table;

(2) then selecting one or more neighboring values for each entry in the priority read retry table starting with the newest successful entry and proceeding chronologically to the oldest successful entry in the priority read retry table; and

(3) then selecting entries in the read retry table according to the set order.

15. The method of claim 10 , performed by one or more of an non-volatile memory (NVM) controller, a solid state device (SSD) controller, and a host device.

16. An apparatus, comprising:

means for generating a priority read retry table of read retry entries based on read retry entries obtained from a separate read retry table of set order;

means for determining a most recent successful read retry entry from the separate read retry table; and

means for populating the priority read retry table by inserting an entry from the read retry table into the priority read retry table, wherein the entry corresponds to the most recent successful read retry entry and is inserted as a first priority entry in the priority read retry table.

17. The apparatus of claim 16 , further comprising means for executing a read recovery procedure within the physical memory array while using the first entry within the priority read retry table as a first candidate entry during the read recovery procedure.

18. The apparatus of claim 17 , further comprising:

means for selecting candidate read retry entries for the read recovery procedure according to a prescribed priority order until a successful read recovery is achieved.

19. The apparatus of claim 18 , further comprising:

means for selecting entries from the priority read retry table for the read recovery procedure starting with a newest entry and proceeding to an oldest entry in the priority read retry table;

means for selecting one or more neighboring values for each entry in the priority read retry table for the read recovery procedure starting with the newest entry and proceeding to the oldest entry in the priority read retry table; and

means for selecting entries in the read retry table for the read recovery procedure according to the set order.

20. The apparatus of claim 16 , wherein the apparatus is one or more of an non-volatile memory (NVM) controller, a solid state device (SSD) controller, and a host device.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2018
From: CHEN, XIAOHENG
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 046955/0076 →