Semiconductor memory device

1. A semiconductor memory device, comprising:

a plurality of control gate electrodes stacked above a substrate; and

a semiconductor layer having as its longitudinal direction a direction perpendicular to the substrate, the semiconductor layer facing the plurality of control gate electrodes,

the semiconductor memory device further comprising:

first and second control gate electrodes stacked sequentially above the substrate;

third and fourth control gate electrodes stacked sequentially above the substrate and facing the first and second control gate electrodes from a first direction;

first through fourth via contacts connected to these first through fourth control gate electrodes;

a wiring line including a contact portion and a lead-out portion, the contact portion extending in the first direction and commonly connected to the second via contact and the fourth via contact, the lead-out portion provided along a second direction intersecting the first direction;

other wiring lines respectively connected to the first via contact and the third via contact; and

a position in the first direction of the first via contact being further from the third control gate electrode than is a center position in the first direction of the first control gate electrode,

a position in the first direction of the second via contact being closer to the fourth control gate electrode than is a center position in the first direction of the second control gate electrode,

a position in the first direction of the third via contact being further from the first control gate electrode than is a center position in the first direction of the third control gate electrode,

a position in the first direction of the fourth via contact being closer to the second control gate electrode than is a center position in the first direction of the fourth control gate electrode,

a position in the first direction of the lead-out portion of the wiring line being between the first via contact and the third via contact, and

the wiring lines connected to the first through fourth via contacts being provided in an identical wiring line layer.

2. The semiconductor memory device according to claim 1 , further comprising:

a plurality of fifth control gate electrodes positioned in a higher layer than the first through fourth control gate electrodes and arranged in the first direction;

a plurality of fifth via contacts connected to the plurality of fifth control gate electrodes; and

further another wiring line commonly connected to the plurality of fifth control gate electrodes via the plurality of fifth via contacts.

3. The semiconductor memory device according to claim 1 , wherein

at least one of the first through fourth control gate electrodes

comprises a first region and a second region arranged in the second direction,

includes a first through hole in the first region,

faces the semiconductor layer at the first through hole, and

is connected to one of the first through fourth via contacts in the second region.

4. The semiconductor memory device according to claim 3 , further comprising:

first and second columnar bodies having as their longitudinal direction the direction perpendicular to the substrate,

wherein the second region is provided with at least two second through holes,

the first and second columnar bodies are respectively inserted in the second through holes, and

positions of the first and second columnar bodies are different from each other in the first direction and the second direction.

5. The semiconductor memory device according to claim 3 , further comprising:

a first columnar body having as its longitudinal direction the direction perpendicular to the substrate,

wherein the second region of the first control gate electrode is provided with a second through hole,

the first columnar body is inserted in the second through hole, and

the first columnar body contacts the second control gate electrode from the second direction.

6. A semiconductor memory device, comprising:

a plurality of control gate electrodes stacked above a substrate; and

a semiconductor layer having as its longitudinal direction a direction perpendicular to the substrate, the semiconductor layer facing the plurality of control gate electrodes,

the semiconductor memory device further comprising:

first and second control gate electrodes stacked sequentially above the substrate;

third and fourth control gate electrodes stacked sequentially above the substrate and facing the first and second control gate electrodes from a first direction;

first through fourth via contacts connected to these first through fourth control gate electrodes;

a wiring line including a contact portion extending in the first direction and commonly connected to the first and third via contacts;

another wiring line connected to the second via contact and including a lead-out portion provided along a second direction intersecting the first direction; and

further another wiring line connected to the fourth via contact and including a lead-out portion provided along the second direction,

a position in the first direction of the first via contact being closer to the third control gate electrode than is a center position in the first direction of the first control gate electrode,

a position in the first direction of the second via contact being further from the fourth control gate electrode than is a center position in the first direction of the second control gate electrode,

a position in the first direction of the third via contact being closer to the first control gate electrode than is a center position in the first direction of the third control gate electrode, and

a position in the first direction of the fourth via contact being further from the second control gate electrode than is a center position in the first direction of the fourth control gate electrode,

positions in the first direction of the first via contact and the third via contact being between the lead-out portions of the wiring lines connected to the second and fourth via contacts, and

the wiring lines connected to the first through fourth via contacts being provided in an identical wiring line layer.

7. The semiconductor memory device according to claim 6 , further comprising:

a plurality of fifth control gate electrodes positioned in a higher layer than the first through fourth control gate electrodes and arranged in the first direction;

a plurality of fifth via contacts connected to the plurality of fifth control gate electrodes; and

further another wiring line commonly connected to the plurality of fifth control gate electrodes via the plurality of fifth via contacts.

8. The semiconductor memory device according to claim 6 , wherein

at least one of the first through fourth control gate electrodes

comprises a first region and a second region arranged in the second direction,

includes a first through hole in the first region,

faces the semiconductor layer at the first through hole, and

is connected to one of the first through fourth via contacts in the second region.

9. The semiconductor memory device according to claim 8 , further comprising:

first and second columnar bodies having as their longitudinal direction the direction perpendicular to the substrate,

wherein the second region is provided with at least two second through holes,

the first and second columnar bodies are respectively inserted in the second through holes, and

positions of the first and second columnar bodies are different from each other in the first direction and the second direction.

10. The semiconductor memory device according to claim 8 , further comprising:

a first columnar body having as its longitudinal direction the direction perpendicular to the substrate,

wherein the second region of the first control gate electrode is provided with a second through hole,

the first columnar body is inserted in the second through hole, and

the first columnar body contacts the second control gate electrode from the second direction.