Thin film transistor substrate and method of fabricating the same

1. A thin film transistor substrate comprising:

a thin film transistor connected to a gate line and a data line on a substrate such that the gate line and the data line intersect each other; and

a light barrier film on the substrate to overlap an active layer of the thin film transistor, wherein the data line is disposed on a same plane as the light barrier film.

2. The thin film transistor substrate according to claim 1 , further comprising:

a pixel electrode connected to the thin film transistor;

a common electrode for generating an electric field together with the pixel electrode; and

a multi-layer insulation film between the common electrode and the data line, wherein the multi-layer insulation film comprises:

a buffer layer on the substrate to cover the light barrier film and the data line;

a gate insulation film on the buffer layer to cover the active layer; and

an interlayer insulation film on the gate insulation film to cover a gate electrode of the thin film transistor.

3. The thin film transistor substrate according to claim 2 , further comprising:

a first passivation film on the interlayer insulation film to cover the common electrode;

a touch sensing line on the first passivation film for interconnecting common electrodes of adjacent sub-pixels such that the common electrode is driven as a touch sensing electrode; and

a second passivation film to cover the touch sensing line,

wherein a drain contact electrode of the thin film transistor is connected to the light barrier film disposed on the substrate and a drain region of the active layer through a drain contact hole penetrated through the first passivation film, the interlayer insulation film, the gate insulation film, and the buffer layer, and

wherein a source contact electrode of the thin film transistor is connected to the data line disposed on the substrate and a source region of the active layer through a source contact hole penetrated through the first passivation film, the interlayer insulation film, the gate insulation film, and the buffer layer.

4. The thin film transistor substrate according to claim 3 , wherein the source and drain contact holes penetrated through the first passivation film have a first width,

wherein the source and drain contact holes penetrated through the interlayer insulation film, the gate insulation film, and the buffer layer have a second width, and

wherein the second width is less than the first width.

5. The thin film transistor substrate according to claim 2 , further comprising:

a touch sensing line on the common electrode to directly contact the common electrode, the touch sensing line interconnecting common electrodes of adjacent sub-pixels such that the common electrode is driven as a touch sensing electrode; and

a passivation film on the interlayer insulation film to cover the common electrode and the touch sensing line,

wherein a drain contact electrode of the thin film transistor is connected to the light barrier film disposed on the substrate and a drain region of the active layer through a drain contact hole penetrated through the interlayer insulation film, the gate insulation film, and the buffer layer, and

wherein a source contact electrode of the thin film transistor is connected to the data line disposed on the substrate and a source region of the active layer through a source contact hole penetrated through the interlayer insulation film, the gate insulation film, and the buffer layer.

6. The thin film transistor substrate according to claim 2 , wherein the thin film transistor comprises:

the active layer having a channel region, a source region, and a drain region;

a gate electrode overlapping the channel region of the active layer on the gate insulation film;

a source contact electrode connected to the source region and the data line under the source region; and

a drain contact electrode connected to the drain region and the light barrier film under drain region.

7. The thin film transistor substrate according to claim 6 , further comprising:

a first passivation film on the interlayer insulation film,

wherein the drain contact electrode is connected to the light barrier film disposed on the substrate and the drain region of the active layer through a drain contact hole is penetrated through the first passivation film, the interlayer insulation film, the gate insulation film, and the buffer layer, and

wherein the source contact electrode is connected to the data line disposed on the substrate and the source region of the active layer through a source contact hole is penetrated through the first passivation film, the interlayer insulation film, the gate insulation film, and the buffer layer.

8. The thin film transistor substrate according to claim 6 , wherein the drain contact electrode is connected to the light barrier film disposed on the substrate and the drain region of the active layer through a drain contact hole is penetrated through the interlayer insulation film, the gate insulation film, and the buffer layer, and

wherein the source contact electrode is connected to the data line disposed on the substrate and the source region of the active layer through a source contact hole is penetrated through the interlayer insulation film, the gate insulation film, and the buffer layer.

9. A thin film transistor substrate comprising:

a thin film transistor connected to a gate line and a data line on a substrate such that the gate line and the data line intersect each other;

a light barrier film on the substrate to overlap an active layer of the thin film transistor;

a pixel electrode connected to the thin film transistor;

a common electrode for generating an electric field together with the pixel electrode; and

a multi-layer insulation film between the common electrode and the data line, the multi-layer insulation film comprising at least a one-layer passivation film made of an organic material, wherein the data line is disposed on a same plane as the light barrier film.

10. The thin film transistor substrate according to claim 9 , wherein the multi-layer insulation film comprises:

a buffer layer on the substrate to cover the light barrier film and the data line;

a gate insulation film on the buffer layer to cover the active layer;

an interlayer insulation film on the gate insulation film to cover a gate electrode of the thin film transistor; and

the passivation film, made of the organic material, disposed on the interlayer insulation film.

11. The thin film transistor substrate according to claim 10 , further comprising:

a touch sensing line for interconnecting common electrodes of adjacent sub-pixels such that the common electrode is driven as a touch sensing electrode,

wherein the touch sensing line is on the common electrode or under the common electrode to directly contact the common electrode.

12. The thin film transistor substrate according to claim 10 , wherein the thin film transistor comprises:

the active layer having a channel region, a source region, and a drain region;

a gate electrode overlapping the channel region of the active layer on the gate insulation film;

a source contact electrode connected to the source region and the data line under the source region; and

a drain contact electrode connected to the drain region and the light barrier film under drain region.

13. The thin film transistor substrate according to claim 12 , wherein the drain contact electrode is connected to the light barrier film disposed on the substrate and the drain region of the active layer through a drain contact hole is penetrated through the passivation film, the interlayer insulation film, the gate insulation film, and the buffer layer, and

wherein the source contact electrode is connected to the data line disposed on the substrate and the source region of the active layer through a source contact hole is penetrated through the passivation film, the interlayer insulation film, the gate insulation film, and the buffer layer.