Decoding algorithm with enhanced parity check matrix and re-encoding scheme for LDPC code

1. A computer-implemented method of decoding a Low Density Parity Check (LDPC) code with an enhanced parity check matrix and a re-encoding scheme to decrease decoding iteration of the LDPC code and shorten decoding latency, comprising the steps of:

A. providing the enhanced parity check matrix which is formed by a plurality of sub-matrixes, wherein a first identity matrix in a specific location;

B. receiving a message part of an original codeword encoded by a generator matrix from the enhanced parity check matrix with at least one bit is corrupted;

C. setting a Log-Likelihood Ratio (LLR) for each bit node of the enhanced parity check matrix while keeping receiving an original parity part of the original codeword;

D. processing hard decision on the message part of the original codeword;

E. encoding the message part of the original codeword by the generator matrix to generate a new codeword having a generated parity part;

F. comparing the original parity part with the generated parity part to find out bits of difference;

G. voting candidate error bits to choose the most probably erratic bits;

H. modifying LLR of the chosen bits to have a modified codeword; and

I. processing a conventional iterative decoding procedure on the modified codeword to have a processed codeword,

wherein the enhanced parity check matrix, H enhanced , has a form of

H enhanced =[H 1 |H 2 ],

wherein each sub-matrix is a zero matrix, an identity matrix or a shifted matrix which has all 1s in an identity matrix shifted to the right side a certain times; arrangement of identity matrixes in H 2 is a dual-diagonal structure; a first column of sub-matrixes in H 2 is close to H 1 ; a first sub-matrix located first from the top of the first column and a last sub-matrix located last from the top of the first column are both identity matrixes or shifted matrixes; sub-matrixes between the first sub-matrix and the last sub-matrix are zero matrixes and the first identity matrix; the first identity matrix is located closer to the last sub-matrix than the first sub-matrix.

2. The computer-implemented method according to claim 1 , further comprising the steps of, after step I:

J. judging if a preset number of iteration is reached or a product of the enhanced parity check matrix and the processed codeword equals zero; and

K. if a result of step J is “no”, repeating the procedure from step D with the processed codeword; if the result of step J is “yes”, outputting a message part of the processed codeword.

3. The computer-implemented method according to claim 1 , wherein the first identity matrix is located next to the last sub-matrix.

4. The computer-implemented method according to claim 1 , wherein the LLR for each bit node is available by

LLR

=

2

σ

2

⁢

y

k

,

where y k is received signal of any one bit in the message part of the original codeword and σ is variance of all received signals; k is any integer.

5. The computer-implemented method according to claim 1 , wherein a voting means works for voting candidate error bits.

6. The computer-implemented method according to claim 1 , wherein the LLR is modified by changing magnitude thereof or sign.

7. The computer-implemented method according to claim 1 , wherein the conventional iterative decoding procedure is Sun-Product Algorithm (SPA).